公开(公告)号：US07994040B2

公开(公告)日：2011-08-09

申请号：US11785023

申请日：2007-04-13

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US20080254579A1

公开(公告)日：2008-10-16

申请号：US11785023

申请日：2007-04-13

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

IPC分类号： H01L21/00 ,  H01L29/94

CPC分类号： H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US08421166B2

公开(公告)日：2013-04-16

申请号：US13175443

申请日：2011-07-01

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Cheng-Ku Chen

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Cheng-Ku Chen

IPC分类号： H01L21/02 ,  H01L27/118 ,  H01L21/76

CPC分类号： H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US07564105B2

公开(公告)日：2009-07-21

申请号：US11094879

申请日：2005-03-30

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang

IPC分类号： H01L27/088

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an active region of the device. A third device has an undoped recessed channel formed in a sidewall of a shallow trench, wherein the undoped recessed channel further has a plurality of edge-fins disposed thereon. Additionally, an extra mask may be added to each device to allow for fabrication of both conventional transistors and FinFET-like transistors on bulk silicon. The extra mask may protect the source and drain areas from recess etching of the silicon substrate. Several methods of fabricating each device are also disclosed.

摘要翻译： 公开了在体硅衬底上的准平面CMOS和FinFET类晶体管器件的类型。 第一器件具有形成在浅沟槽侧壁中的掺杂和凹陷沟道。 第二装置具有掺杂的凹陷通道，并且具有并置在装置的有源区域的边缘上的多个边缘鳍片。 第三装置具有形成在浅沟槽的侧壁中的未掺杂的凹陷通道，其中未掺杂的凹陷通道还具有设置在其上的多个边缘翅片。 此外，可以向每个器件添加额外的掩模，以允许在体硅上制造常规晶体管和FinFET类晶体管。 额外的掩模可以保护源极和漏极区域免受硅衬底的凹陷蚀刻。 还公开了制造每个器件的几种方法。

公开(公告)号：US07371634B2

公开(公告)日：2008-05-13

申请号：US11048485

申请日：2005-01-31

申请人： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

发明人： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/0212 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/3127 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/78 ,  H01L29/7843 ,  Y02P80/30

摘要： A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

摘要翻译： 一种包括接触蚀刻停止层和接触孔形成方法的半导体器件，用于减少下面的材料损耗和改进的器件性能，所述方法包括提供包括包括CMOS器件，STI结构和金属硅化物区域的有源区的半导体衬底; 在有源区上形成氟掺杂的非晶碳层; 在氟掺杂的非晶碳层上形成PMD层; 在PMD层中干蚀刻接触孔以暴露氟掺杂的无定形碳层; 并根据干法汽提法除去氟掺杂的无定形碳层。

公开(公告)号：US20060170058A1

公开(公告)日：2006-08-03

申请号：US11048485

申请日：2005-01-31

申请人： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

发明人： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/0212 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/3127 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/78 ,  H01L29/7843 ,  Y02P80/30

摘要： A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

摘要翻译： 一种包括接触蚀刻停止层和接触孔形成方法的半导体器件，用于减少下面的材料损耗和改进的器件性能，所述方法包括提供包括包括CMOS器件，STI结构和金属硅化物区域的有源区的半导体衬底; 在有源区上形成氟掺杂的非晶碳层; 在氟掺杂的非晶碳层上形成PMD层; 在PMD层中干蚀刻接触孔以暴露氟掺杂的无定形碳层; 并根据干法汽提法除去氟掺杂的无定形碳层。

公开(公告)号：US20050239254A1

公开(公告)日：2005-10-27

申请号：US11094879

申请日：2005-03-30

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an active region of the device. A third device has an undoped recessed channel formed in a sidewall of a shallow trench, wherein the undoped recessed channel further has a plurality of edge-fins disposed thereon. Additionally, an extra mask may be added to each device to allow for fabrication of both conventional transistors and FinFET-like transistors on bulk silicon. The extra mask may protect the source and drain areas from recess etching of the silicon substrate. Several methods of fabricating each device are also disclosed.

摘要翻译： 公开了在体硅衬底上的准平面CMOS和FinFET类晶体管器件的类型。 第一器件具有形成在浅沟槽侧壁中的掺杂和凹陷沟道。 第二装置具有掺杂的凹陷通道，并且具有并置在装置的有源区域的边缘上的多个边缘鳍片。 第三装置具有形成在浅沟槽的侧壁中的未掺杂的凹陷通道，其中未掺杂的凹陷通道还具有设置在其上的多个边缘翅片。 此外，可以向每个器件添加额外的掩模，以允许在体硅上制造常规晶体管和FinFET类晶体管。 额外的掩模可以保护源极和漏极区域免受硅衬底的凹陷蚀刻。 还公开了制造每个器件的几种方法。

公开(公告)号：US08969922B2

公开(公告)日：2015-03-03

申请号：US13368960

申请日：2012-02-08

申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

IPC分类号： H01L27/118 ,  H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括半导体衬底，其包括设置在第一器件区域中的第一器件，所述第一器件包括第一栅极结构，形成在第一栅极结构的侧壁上的第一栅极间隔物，以及第一源极和漏极特征， 设置在第二器件区域中，第二器件包括第二栅极结构，形成在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 半导体器件还包括设置在第一和第二栅极间隔物上的接触蚀刻停止层（CESL）和布置在第一和第二源极和漏极特征上的互连结构。 互连结构与第一和第二源极和漏极特征电接触并与CESL接触。

公开(公告)号：US20130200461A1

公开(公告)日：2013-08-08

申请号：US13368960

申请日：2012-02-08

申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Mu-Chi Chiang ,  Yao-Kwang Wu ,  Bi-Fen Wu ,  Huan-Just Lin ,  Hsiao-Tzu Lu ,  Hui-Chi Huang

IPC分类号： H01L27/092 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括半导体衬底，其包括设置在第一器件区域中的第一器件，所述第一器件包括第一栅极结构，形成在第一栅极结构的侧壁上的第一栅极间隔物，以及第一源极和漏极特征， 设置在第二器件区域中，第二器件包括第二栅极结构，形成在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 半导体器件还包括设置在第一和第二栅极间隔物上的接触蚀刻停止层（CESL）和布置在第一和第二源极和漏极特征上的互连结构。 互连结构与第一和第二源极和漏极特征电接触并与CESL接触。

公开(公告)号：US06235600B1

公开(公告)日：2001-05-22

申请号：US09531403

申请日：2000-03-20

申请人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

发明人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

摘要： A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

摘要翻译： 已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。 该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。 在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料 当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。