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    VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD
    1.
    发明申请
    VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD 审中-公开
    具有改进的负载调节和电压调节方法的电压调节器

    公开(公告)号：US20130148456A1

    公开(公告)日：2013-06-13

    申请号：US13545877

    申请日：2012-07-10

    申请人： Min-Hyung CHO ,  Yi-Gyeong KIM ,  Tae Moon ROH ,  Woo Seok YANG ,  Jong-Kee KWON ,  Jongdae KIM

    发明人： Min-Hyung CHO ,  Yi-Gyeong KIM ,  Tae Moon ROH ,  Woo Seok YANG ,  Jong-Kee KWON ,  Jongdae KIM

    IPC分类号： G05F1/10 ,  G11C5/14

    CPC分类号： G11C5/145 ,  H02M3/073 ,  H02M2001/0045

    摘要： Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics.

    摘要翻译： 提供了使用电荷泵的电压供给电路。 当通过调节器接收电荷泵的操作电源电压时，电压供应电路根据电荷泵电压发生器的负载变化（负载调节特性）来增强电荷泵输出电压波动特性。 电压供给电路被配置为将电荷泵输出电压的波动反馈到电荷泵电压调节器。 通过电荷泵的输出电压的波动补偿电荷泵输出电压的波动，从而有效提高负载调节特性。

    SOUND DETECTING CIRCUIT AND AMPLIFIER CIRCUIT THEREOF
    2.
    发明申请
    SOUND DETECTING CIRCUIT AND AMPLIFIER CIRCUIT THEREOF 有权
    声音检测电路和放大器电路

    公开(公告)号：US20130099868A1

    公开(公告)日：2013-04-25

    申请号：US13531437

    申请日：2012-06-22

    申请人： Yi-Gyeong KIM ,  Min-Hyung CHO ,  Tae Moon ROH ,  Jong-Kee KWON ,  Woo Seok YANG ,  Jongdae KIM

    发明人： Yi-Gyeong KIM ,  Min-Hyung CHO ,  Tae Moon ROH ,  Jong-Kee KWON ,  Woo Seok YANG ,  Jongdae KIM

    IPC分类号： H03F3/04

    CPC分类号： H03F3/08

    摘要： Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

    摘要翻译： 公开了一种声音检测电路，其包括：感测单元，被配置为响应于声音信号的声压级产生AC信号; 放大单元，被配置为放大AC信号; 以及偏置电压产生单元，被配置为产生要提供给所述放大单元的偏置电压。 偏置电压产生单元包括被配置为提供功率电流的电流源; 以及电流电压转换电路，被配置为将功率电流转换成偏置电压并且减少由于功率电流引起的噪声。

    ANALOG-DIGITAL CONVERTER AND CONVERTING METHOD USING CLOCK DELAY
    3.
    发明申请
    ANALOG-DIGITAL CONVERTER AND CONVERTING METHOD USING CLOCK DELAY 失效
    模拟数字转换器和使用时钟延迟的转换方法

    公开(公告)号：US20130057424A1

    公开(公告)日：2013-03-07

    申请号：US13593301

    申请日：2012-08-23

    申请人： Young-deuk JEON ,  Woo Seok YANG ,  Tae Moon ROH ,  Jong-Kee KWON ,  Jongdae KIM

    发明人： Young-deuk JEON ,  Woo Seok YANG ,  Tae Moon ROH ,  Jong-Kee KWON ,  Jongdae KIM

    IPC分类号： H03M1/34 ,  H03M1/12

    CPC分类号： H03M1/462

    摘要： The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.

    摘要翻译： 本发明构思涉及一种模数转换器。 模拟数字转换器包括产生时钟信号的时钟产生单元; 时钟延迟调整单元，根据控制信号将第一时钟信号中的一个输出到第K个时钟信号; 输出模拟信号和参考信号之间的差的电容数字 - 模拟转换单元; 比较单元，响应于时钟延迟调整单元的输出，判定电容数字 - 模拟转换单元的输出是0，正数还是负数; 以及SAR逻辑单元，响应于时钟延迟调整单元的输出，将比较单元的输出传送到电容数字 - 模拟转换单元，并执行逐次逼近操作以输出N位数字信号。

    IMAGE PROCESSING DEVICE
    4.
    发明申请
    IMAGE PROCESSING DEVICE 审中-公开
    图像处理装置

    公开(公告)号：US20100135396A1

    公开(公告)日：2010-06-03

    申请号：US12540722

    申请日：2009-08-13

    申请人： Jung Hee SUK ,  Chun-Gi LYUH ,  Tae Moon ROH ,  Jongdae KIM

    发明人： Jung Hee SUK ,  Chun-Gi LYUH ,  Tae Moon ROH ,  Jongdae KIM

    IPC分类号： H04N7/26

    CPC分类号： H04N19/436 ,  H04N19/109 ,  H04N19/147 ,  H04N19/176 ,  H04N19/61

    摘要： Provided is an image processing device. The image processing device includes: a plurality of operation units; and a controller unit storing an occurred bit amount to calculate a rate-distortion cost value and transmitting the occurred bit amount to each of the plurality of operation units, wherein at least one of the plurality of operation units calculates each distortion value with respect to a plurality of encoding modes and calculates each rate-distortion cost value with respect to the plurality of encoding modes using the calculated each distortion value and occurred bit amount.

    摘要翻译： 提供了一种图像处理装置。 图像处理装置包括：多个操作单元; 以及控制器单元，存储发生的比特量以计算速率失真成本值，并将所发生的比特量发送到多个操作单元中的每一个，其中多个操作单元中的至少一个针对一个操作单元计算每个失真值 多个编码模式，并且使用所计算的每个失真值和发生的位量来计算关于多个编码模式的每个速率 - 失真成本值。

    RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME
    5.
    发明申请
    RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME 有权
    可重构算术单元和具有相同功能的高效处理器

    公开(公告)号：US20090150471A1

    公开(公告)日：2009-06-11

    申请号：US12136107

    申请日：2008-06-10

    申请人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： G06F17/10

    CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

    摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

    摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

    DUAL STRUCTURE FINFET AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    DUAL STRUCTURE FINFET AND METHOD OF MANUFACTURING THE SAME 有权
    双结构FINFET及其制造方法

    公开(公告)号：US20080135935A1

    公开(公告)日：2008-06-12

    申请号：US11924903

    申请日：2007-10-26

    申请人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

    摘要翻译： 提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。 因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。 此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联 源极和漏极的电阻分量以增加电流驱动能力。

    LOW-POWER CLOCK GATING CIRCUIT
    7.
    发明申请
    LOW-POWER CLOCK GATING CIRCUIT 有权
    低功率时钟提升电路

    公开(公告)号：US20080129359A1

    公开(公告)日：2008-06-05

    申请号：US11945387

    申请日：2007-11-27

    申请人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： H03K3/356

    CPC分类号： H03K3/0375

    摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

    摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

    BUS BRIDGE APPARATUS
    8.
    发明申请
    BUS BRIDGE APPARATUS 审中-公开

    公开(公告)号：US20130166801A1

    公开(公告)日：2013-06-27

    申请号：US13620294

    申请日：2012-09-14

    申请人： Ik Jae Jae CHUN ,  Chun-Gi LYUH ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    发明人： Ik Jae Jae CHUN ,  Chun-Gi LYUH ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4059

    摘要： Disclosed is a bus bridge apparatus may prevent a transfer performance from being lowered due to bus protocol performance mismatch between interconnections. The bus bridge apparatus is used to transfer data to a slave device of a network-based interconnection from a master device of a bus-based interconnection, data of the master device may be buffered by an internal buffer, and may then be transferred to the slave device. At this time, lowering of a transfer efficiency may be prevented by converting a transfer timing of addresses and data to be optimized to a transfer protocol of the network-based interconnection through a protocol converter.

    摘要翻译： 公开了一种总线桥接装置可以防止由于互连之间的总线协议性能不匹配而导致传输性能降低。 总线桥装置用于从基于总线的互连的主设备将数据传送到基于网络的互连的从设备，主设备的数据可以由内部缓冲器缓冲，然后可以被传送到 从设备。 此时，可以通过协议转换器将要优化的地址和数据的传送定时转换为基于网络的互连的传输协议来防止传输效率的降低。

    FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME
    9.
    发明申请
    FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME 审中-公开
    特征向量分类器和识别装置使用它

    公开(公告)号：US20130156319A1

    公开(公告)日：2013-06-20

    申请号：US13550833

    申请日：2012-07-17

    申请人： Chun-Gi LYUH ,  Ik Jae CHUN ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    发明人： Chun-Gi LYUH ,  Ik Jae CHUN ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    IPC分类号： G06K9/46

    CPC分类号： G06K9/6269

    摘要： Provided are a feature vector extractor and a recognition device using the same. The feature vector classifier includes a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; and a feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image. Thus, during extraction and classification of a feature vector, time required for the extraction and classification and the size of hardware required are significantly reduced.

    摘要翻译： 提供了一种特征向量提取器和使用其的识别装置。 特征向量分类器包括：特征向量提取器，被配置为从输入图像生成特征向量和归一化值，并输出特征向量和归一化值; 以及特征矢量分类器，其被配置为基于归一化值对特征向量进行归一化，并且对归一化特征向量进行分类以识别输入图像。 因此，在特征向量的提取和分类期间，提取和分类所需的时间以及所需的硬件的大小显着降低。