公开(公告)号：US20080135935A1

公开(公告)日：2008-06-12

申请号：US11924903

申请日：2007-10-26

申请人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

摘要翻译： 提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。 因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。 此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联 源极和漏极的电阻分量以增加电流驱动能力。

公开(公告)号：US20100019321A1

公开(公告)日：2010-01-28

申请号：US12556666

申请日：2009-09-10

申请人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US20090150471A1

公开(公告)日：2009-06-11

申请号：US12136107

申请日：2008-06-10

申请人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： G06F17/10

CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

公开(公告)号：US20080129359A1

公开(公告)日：2008-06-05

申请号：US11945387

申请日：2007-11-27

申请人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： H03K3/356

CPC分类号： H03K3/0375

摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

公开(公告)号：US20080294875A1

公开(公告)日：2008-11-27

申请号：US12045844

申请日：2008-03-11

申请人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

发明人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F15/8007

摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

公开(公告)号：US20100257342A1

公开(公告)日：2010-10-07

申请号：US12817407

申请日：2010-06-17

申请人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

发明人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

IPC分类号： G06F9/302

CPC分类号： G06F15/8007

摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

公开(公告)号：US20090144523A1

公开(公告)日：2009-06-04

申请号：US12174988

申请日：2008-07-17

申请人： Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： G06F15/8007 ,  G06F9/30181 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A multiple-single instruction multiple data (SIMD) processor and an arithmetic method using the same are disclosed. When various arithmetic operations should be individually carried out by SIMD arithmetic units, control right is sub-divided to perform the arithmetic operations, such that the time of the arithmetic operations can be shortened and the efficiency thereof can be raised. When sub-divided control is not required, the control right is withdrawn and the arithmetic operations are carried out using a minimum number of program memories and a minimum number of SIMD arithmetic units, such that memory and power consumption thereof can be reduced.

摘要翻译： 公开了一种多单指令多数据（SIMD）处理器及其运算方法。 当通过SIMD算术单元分别进行各种算术运算时，控制权被细分，进行算术运算，可以缩短算术运算的时间，提高效率。 当不需要分分割控制时，撤回控制权，并且使用最少数量的程序存储器和最小数量的SIMD运算单元执行算术运算，从而可以减少存储器和功耗。

公开(公告)号：US20090138645A1

公开(公告)日：2009-05-28

申请号：US12171397

申请日：2008-07-11

申请人： Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： G06F13/28

CPC分类号： G06F13/1657 ,  G06F13/28

摘要： Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.

摘要翻译： 提供了一种用于多媒体系统的片上系统（SoC）系统，能够高速传输大量的多媒体数据和处理器来快速控制外围设备。 SoC系统包括一个处理器; 多个外围设备; 多个物理划分的存储器; 用于将控制信号从处理器传送到外围设备和存储器的控制总线; 用于在处理器，外围设备和存储器之间传送数据的数据总线; 用于将控制总线和数据总线耦合到处理器的桥; 耦合到控制总线并控制每个存储器的多个存储器控制器; 耦合到数据总线和控制总线的直接存储器访问（DMA）控制器，并控制外围设备和存储器之间的数据传输; 以及耦合在DMA控制器和存储器控制器之间的矩阵开关，并且能够同时进行多个存储器访问。

公开(公告)号：US20080292001A1

公开(公告)日：2008-11-27

申请号：US12105745

申请日：2008-04-18

申请人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Jung Hoon KIM

发明人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Jung Hoon KIM

IPC分类号： H04N7/26

CPC分类号： H04N19/00521 ,  H04N19/102 ,  H04N19/122 ,  H04N19/134 ,  H04N19/436 ,  H04N19/57 ,  H04N19/61 ,  H04N19/86

摘要： Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

摘要翻译： 提供了一种用于计算能够相对于多个当前帧宏块同时并行计算SAD值的可变块的运动估计的绝对差（SAD）的装置和方法。 该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算设置在多个串行当前帧宏块中的至少一个像素的SAD值，本地存储器 包括当前帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，以及将数据发送到在PE阵列单元中提供的每个PE，以及用于为在本地提供的数据进行命令的控制器 要发送对应于至少一个像素的存储器，其中PE阵列单元中提供的每个PE执行计算。

公开(公告)号：US20130148456A1

公开(公告)日：2013-06-13

申请号：US13545877

申请日：2012-07-10

申请人： Min-Hyung CHO ,  Yi-Gyeong KIM ,  Tae Moon ROH ,  Woo Seok YANG ,  Jong-Kee KWON ,  Jongdae KIM

发明人： Min-Hyung CHO ,  Yi-Gyeong KIM ,  Tae Moon ROH ,  Woo Seok YANG ,  Jong-Kee KWON ,  Jongdae KIM

IPC分类号： G05F1/10 ,  G11C5/14

CPC分类号： G11C5/145 ,  H02M3/073 ,  H02M2001/0045

摘要： Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics.

摘要翻译： 提供了使用电荷泵的电压供给电路。 当通过调节器接收电荷泵的操作电源电压时，电压供应电路根据电荷泵电压发生器的负载变化（负载调节特性）来增强电荷泵输出电压波动特性。 电压供给电路被配置为将电荷泵输出电压的波动反馈到电荷泵电压调节器。 通过电荷泵的输出电压的波动补偿电荷泵输出电压的波动，从而有效提高负载调节特性。