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    Indolestyryl compound and high density recording media utilizing the same
    4.
    发明申请
    Indolestyryl compound and high density recording media utilizing the same 有权
    吲哚美辛化合物和使用其的高密度记录介质

    公开(公告)号：US20070219377A1

    公开(公告)日：2007-09-20

    申请号：US11410967

    申请日：2006-04-26

    申请人： Shin-Shin Wang ,  Chien-Wen Chen ,  Jong-Lieh Yang ,  Chii-Chang Lai ,  Hui-Ping Tsai ,  Wen-Ping Chu ,  Wen-Yih Liao ,  Chien-Liang Huang ,  Tzuan-Ren Jeng ,  Ching-Yu Hsieh ,  An-Tse Lee

    发明人： Shin-Shin Wang ,  Chien-Wen Chen ,  Jong-Lieh Yang ,  Chii-Chang Lai ,  Hui-Ping Tsai ,  Wen-Ping Chu ,  Wen-Yih Liao ,  Chien-Liang Huang ,  Tzuan-Ren Jeng ,  Ching-Yu Hsieh ,  An-Tse Lee

    IPC分类号： C07D277/62

    CPC分类号： C07D209/14 ,  C07D277/64 ,  G11B7/2467 ,  G11B7/2472 ,  G11B7/2478 ,  G11B7/2495 ,  G11B2007/24612

    摘要： An indolestyryl compound. The indolestyryl compound has formula (I): wherein Z1 comprises benzene, naphthalene, or heterocyclic ring containing O, S, or N, R2 comprises H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, sulfuric ester, amide, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R3, R4, R5, and R6 comprise H, alkyl, aralkyl, or heterocyclic ring containing O, S, or N, R7 and R8 comprise H or alkyl, R10 comprises H, alkyl, halogen atoms, nitro, hydroxyl, amino, ester, or substituted or non-substituted sulfonyl, W comprises carbon or nitrogen, Y comprises carbon, oxygen, sulfur, selenium, —NR, or —C(CH3)2, m is 1˜3, and X1 comprises an anionic group or an anionic organometallic complex, wherein R3 and R4 are joined to a nitrogen atom or R5 and R6 are joined together to form a ring, and R bonded to nitrogen is C1-5 alkyl.

    摘要翻译： 吲哚满甲基化合物。 吲哚美辛酰化合物具有式（I）：其中Z 1包括含有O，S或N的苯，萘或杂环，R 2包括H，卤素原子， C 1-5烷基，硝基，酯，羧基，磺基，磺酰胺，硫酸酯，酰胺，C 1-3烷氧基，氨基，烷基氨基，氰基，C C 1-6烷基磺酰基或C 2-7烷氧基羰基，R 3，R 4，R 5 R 6和R 6包含H，烷基，芳烷基或含有O，S或N，R 7和R 8的杂环， 包括H或烷基，R 10包含H，烷基，卤素原子，硝基，羟基，氨基，酯或取代或未取代的磺酰基，W包括碳或氮，Y包括碳， 氧，硫，硒，-NR或-C（CH 3）2，m为1〜3，X 1为 阴离子基团或阴离子有机金属络合物，其中R 3和R 4连接到氮原子或R 5 >和R 6连接在一起形成环，并且与氮键合的R 1为C 1-5烷基。

    Semiconductor device design method, system and computer program product
    9.
    发明授权
    Semiconductor device design method, system and computer program product 有权
    半导体器件设计方法，系统和计算机程序产品

    公开(公告)号：US08904326B2

    公开(公告)日：2014-12-02

    申请号：US13539258

    申请日：2012-06-29

    申请人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

    发明人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

    摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

    摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。 由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。 基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

    Method and system for layout parasitic estimation
    10.
    发明授权
    Method and system for layout parasitic estimation 有权
    布局寄生估计方法和系统

    公开(公告)号：US08806414B2

    公开(公告)日：2014-08-12

    申请号：US13484480

    申请日：2012-05-31

    申请人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

    发明人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/82

    摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

    摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。