-
公开(公告)号：US20110248328A1
公开(公告)日：2011-10-13
申请号：US12757172
申请日：2010-04-09
申请人： Ming-Huei Shen , Tsun Kai Tsao , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Ming-Huei Shen , Tsun Kai Tsao , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.
摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底上的第一浮置栅极，浮置栅极具有凹面侧面; 第一个浮动门上的第一个控制门; 与所述第一控制栅极相邻的第一间隔件; 与所述第一浮动栅极的第一侧相邻的第一字线，具有第一距离; 以及与所述第一浮动栅极的第二侧相邻的擦除栅极，其具有小于所述第一距离的第二距离，所述第二侧与所述第一侧相对。
-
公开(公告)号：US08273625B2
公开(公告)日：2012-09-25
申请号：US12757172
申请日：2010-04-09
申请人： Ming-Huei Shen , Tsun-Kai Tsao , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Ming-Huei Shen , Tsun-Kai Tsao , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.
摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底上的第一浮置栅极，浮置栅极具有凹面侧面; 第一个浮动门上的第一个控制门; 与所述第一控制栅极相邻的第一间隔件; 与所述第一浮动栅极的第一侧相邻的第一字线，具有第一距离; 以及与所述第一浮动栅极的第二侧相邻的擦除栅极，其具有小于所述第一距离的第二距离，所述第二侧与所述第一侧相对。
-
公开(公告)号：US08685783B2
公开(公告)日：2014-04-01
申请号：US12913117
申请日：2010-10-27
IPC分类号： H01L21/00
CPC分类号： H01L45/1253 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer. Portions of the electrode layer and the phase change layer are removed by a chemical-mechanical-polishing process to form a phase change region having a remaining portion of the phase change layer and to form an electrode region having a remaining portion of the electrode layer.
摘要翻译： 在具有第一电介质层，第二电介质层和第三电介质层的第一结构上，通过第三电介质层和第二电介质层形成表冠。 在第一结构上沉积第四电介质层，从而在冠部上方。 去除第四电介质层的一部分以形成具有第四电介质层的剩余部分的第一间隔物。 在去除第四介电层的部分期间，第三电层的一部分也被去除，导致具有第三介电层的剩余部分的第二间隔物。 由此形成第二结构。 相变材料层沉积在第二结构上。 电极层沉积在相变层上。 通过化学机械抛光工艺除去电极层和相变层的一部分，形成具有相变层的剩余部分的相变区域，并形成具有电极层的剩余部分的电极区域。
-
公开(公告)号：US20130048936A1
公开(公告)日：2013-02-28
申请号：US13216369
申请日：2011-08-24
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1683
摘要： A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.
摘要翻译： 公开了一种细间距相变随机存取存储器（PCRAM）设计及其制造方法。 一个实施例是相变存储器（PCM）单元，其包括限定矩形反应区域的间隔件和设置在反应区域内的相变材料层。 PCM单元进一步包括设置在GST膜层之上并在由间隔物限定的区域内的保护层; 以及设置在所述保护层和间隔物上方的覆盖层。
-
公开(公告)号：US08932900B2
公开(公告)日：2015-01-13
申请号：US13216369
申请日：2011-08-24
IPC分类号： H01L21/8239 , H01L45/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1683
摘要： A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.
摘要翻译： 公开了一种细间距相变随机存取存储器（“PCRAM”）设计及其制造方法。 一个实施例是相变存储器（“PCM”）单元，其包括限定矩形反应区域的间隔区和设置在反应区域内的相变材料层。 PCM单元进一步包括设置在GST膜层之上并在由间隔物限定的区域内的保护层; 以及设置在所述保护层和间隔物上方的覆盖层。
-
公开(公告)号：US08445953B2
公开(公告)日：2013-05-21
申请号：US12765658
申请日：2010-04-22
申请人： Ming-Hui Shen , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Tsun Kai Tsao
发明人： Ming-Hui Shen , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Tsun Kai Tsao
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/823468 , H01L27/11521
摘要： A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.
摘要翻译： 提供闪存单元结构。 半导体结构包括半导体衬底，覆盖半导体衬底的浮动栅极，与浮动栅极相邻的字线，与浮动栅极相对的与字线相对的擦除栅极，设置在浮置栅极之间的第一侧壁 栅极和字线，以及设置在浮置栅极和擦除栅极之间的第二侧壁。 第一侧壁具有第一特征，第二侧壁具有第二特征。 第一个特征与第二个特征不同。
-
公开(公告)号：US20110006355A1
公开(公告)日：2011-01-13
申请号：US12765658
申请日：2010-04-22
申请人： Ming-Hui Shen , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Tsun Kai Tsao
发明人： Ming-Hui Shen , Shih-Chang Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Tsun Kai Tsao
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/823468 , H01L27/11521
摘要： A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.
摘要翻译： 提供闪存单元结构。 半导体结构包括半导体衬底，覆盖半导体衬底的浮动栅极，与浮动栅极相邻的字线，与浮动栅极相对的与字线相对的擦除栅极，设置在浮置栅极之间的第一侧壁 栅极和字线，以及设置在浮置栅极和擦除栅极之间的第二侧壁。 第一侧壁具有第一特征，第二侧壁具有第二特征。 第一个特征与第二个特征不同。
-
公开(公告)号：US08288750B2
公开(公告)日：2012-10-16
申请号：US12770344
申请日：2010-04-29
申请人： Ming-Huei Shen , Shih-Chang Liu , Chia-Shiung Tsai
发明人： Ming-Huei Shen , Shih-Chang Liu , Chia-Shiung Tsai
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16
摘要： A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.
摘要翻译： 提供一种半导体器件，其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件，其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间，以及形成在加热元件上的相变元件，其中相变元件包括 基本无定形背景和活性区域，该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。
-
公开(公告)号：US20110266511A1
公开(公告)日：2011-11-03
申请号：US12770344
申请日：2010-04-29
申请人： Ming-Huei Shen , Shih-Chang Liu , Chia-Shiung Tsai
发明人： Ming-Huei Shen , Shih-Chang Liu , Chia-Shiung Tsai
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16
摘要： A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.
摘要翻译： 提供一种半导体器件，其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件，其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间，以及形成在加热元件上的相变元件，其中相变元件包括 基本无定形背景和活性区域，该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。
-
公开(公告)号：US07153755B2
公开(公告)日：2006-12-26
申请号：US11044813
申请日：2005-01-26
申请人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
发明人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/10894 , H01L27/11
摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.
摘要翻译： 提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。 该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。
-
-
-
-
-
-
-
-
-
搜索结果
61 条记录 (耗时 0.107 秒)
