Structure and method for a high-speed semiconductor device having a Ge channel layer
    1.
    发明授权
    Structure and method for a high-speed semiconductor device having a Ge channel layer 有权
    具有Ge沟道层的高速半导体器件的结构和方法

    公开(公告)号:US08436336B2

    公开(公告)日:2013-05-07

    申请号:US11877186

    申请日:2007-10-23

    IPC分类号: H01L29/06

    摘要: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

    摘要翻译: 本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。 在本发明的一个方面,提供了应变的Ge沟道MOSFET。 应变Ge沟道MOSFET包括Ge含量在50-95%之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。 在应变Ge通道上形成栅极结构,于是形成具有在体积Si上增加的性能的MOSFET。 在本发明的另一实施例中,包括松弛的Ge沟道层和虚拟衬底的半导体结构,其中放宽的Ge沟道层设置在虚拟衬底之上。 在本发明的另一方面,提供了一种放宽的Ge沟道MOSFET。 该方法包括提供具有约100%的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

    Structure and method for a high-speed semiconductor device having a Ge channel layer
    2.
    发明授权
    Structure and method for a high-speed semiconductor device having a Ge channel layer 有权
    具有Ge沟道层的高速半导体器件的结构和方法

    公开(公告)号:US07301180B2

    公开(公告)日:2007-11-27

    申请号:US10173986

    申请日:2002-06-18

    IPC分类号: H01L31/0328

    摘要: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

    摘要翻译: 本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。 在本发明的一个方面,提供了应变的Ge沟道MOSFET。 应变Ge沟道MOSFET包括Ge含量在50-95%之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。 在应变Ge通道上形成栅极结构,于是形成具有在体积Si上增加的性能的MOSFET。 在本发明的另一实施例中,包括松弛的Ge沟道层和虚拟衬底的半导体结构,其中放宽的Ge沟道层设置在虚拟衬底之上。 在本发明的另一方面,提供了一种放宽的Ge沟道MOSFET。 该方法包括提供具有约100%的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

    Formation of planar strained layers
    4.
    发明授权
    Formation of planar strained layers 失效
    平面应变层的形成

    公开(公告)号:US06730551B2

    公开(公告)日:2004-05-04

    申请号:US10211126

    申请日:2002-08-02

    IPC分类号: H01L21337

    摘要: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.

    摘要翻译: 一种用于形成结构的结构和方法,所述方法包括形成压缩应变半导体层,所述压应变层具有大于或等于0.25%的应变。 在压缩应变层上形成拉伸应变半导体层。 压缩应变层基本上是平面的,具有表面粗糙度,其特征在于:(i)平均波长大于压缩应变层中的载体的平均波长或(ii)平均高度小于10nm。

    STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER
    5.
    发明申请
    STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER 有权
    具有Ge通道层的高速半导体器件的结构和方法

    公开(公告)号:US20080128747A1

    公开(公告)日:2008-06-05

    申请号:US11877186

    申请日:2007-10-23

    IPC分类号: H01L29/778 H01L21/336

    摘要: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

    摘要翻译: 本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。 在本发明的一个方面,提供了应变的Ge沟道MOSFET。 应变Ge沟道MOSFET包括Ge含量在50-95%之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。 在应变Ge通道上形成栅极结构,于是形成具有在体积Si上增加的性能的MOSFET。 在本发明的另一实施例中,包括松弛的Ge沟道层和虚拟衬底的半导体结构,其中放宽的Ge沟道层设置在虚拟衬底之上。 在本发明的另一方面,提供了一种放宽的Ge沟道MOSFET。 该方法包括提供具有约100%的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

    Structures with planar strained layers
    6.
    发明授权
    Structures with planar strained layers 失效
    具有平面应变层的结构

    公开(公告)号:US07141820B2

    公开(公告)日:2006-11-28

    申请号:US10788741

    申请日:2004-02-27

    IPC分类号: H01L29/04

    摘要: A structure including a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer may be formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer and/or (ii) having an average height less than 10 nm.

    摘要翻译: 包括压缩应变半导体层的结构,该压缩应变层具有大于或等于0.25%的应变。 可以在压缩应变层上形成拉伸应变半导体层。 压缩应变层基本上是平面的,具有表面粗糙度,其特征在于(i)平均波长大于压缩应变层中的载体的平均波长,和/或(ii)平均高度小于10nm。

    Semiconductor devices having strained dual channel layers
    7.
    发明授权
    Semiconductor devices having strained dual channel layers 有权
    具有应变双通道层的半导体器件

    公开(公告)号:US07138310B2

    公开(公告)日:2006-11-21

    申请号:US10456926

    申请日:2003-06-06

    IPC分类号: H01L21/8238

    摘要: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

    摘要翻译: 半导体结构包括锗浓度为至少10原子%的应变诱导基底层。 半导体结构还包括在应变诱导基底层上的压缩应变层。 压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点,并且具有小于其临界厚度的厚度。 半导体结构还包括在压缩应变层上的拉伸应变层。 拉伸应变层可以由厚度小于其临界厚度的硅形成。 一种用于制造半导体结构的方法包括:提供衬底,在衬底上提供压缩应变半导体,在衬底附近沉积拉伸应变半导体,直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度 的拉伸应变半导体,在第一区域上形成n沟道器件,并在第二区域上形成p沟道器件。

    Methods of fabricating semiconductor devices having strained dual channel layers
    8.
    发明授权
    Methods of fabricating semiconductor devices having strained dual channel layers 有权
    制造具有应变双通道层的半导体器件的方法

    公开(公告)号:US07566606B2

    公开(公告)日:2009-07-28

    申请号:US11544245

    申请日:2006-10-06

    IPC分类号: H01L21/00

    摘要: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

    摘要翻译: 半导体结构包括锗浓度为至少10原子%的应变诱导基底层。 半导体结构还包括在应变诱导基底层上的压缩应变层。 压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点,并且具有小于其临界厚度的厚度。 半导体结构还包括在压缩应变层上的拉伸应变层。 拉伸应变层可以由厚度小于其临界厚度的硅形成。 一种用于制造半导体结构的方法包括:提供衬底,在衬底上提供压缩应变半导体,在衬底附近沉积拉伸应变半导体,直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度 的拉伸应变半导体,在第一区域上形成n沟道器件,并在第二区域上形成p沟道器件。