公开(公告)号：US08456126B2

公开(公告)日：2013-06-04

申请号：US13044000

申请日：2011-03-09

申请人： Mitsuaki Tate ,  Yasushi Ishii ,  Masamichi Kihara

发明人： Mitsuaki Tate ,  Yasushi Ishii ,  Masamichi Kihara

IPC分类号： G05B19/416 ,  G05B19/35

CPC分类号： G05B19/351 ,  G05B11/26 ,  G05B2219/41217 ,  H02P23/20

摘要： There is provided a motor control system and motor control method which can shorten settling time by restraining vibration and deviation relative to an advancing direction during operation. Moreover, according to the present invention, it is possible to cause a motor to be operated with an ideal track and, since it is possible to always monitor a present position, it is made easy to cause a plurality of axes to be synchronously operated. The motor control system is provided with a unit generating command waveforms from a jerk data which has significant effects on the vibration relative to the advancing direction, and a unit performing a real time real position control of regenerating future command waveforms according to a deviation amount, while always performing jerk-limit, whereby the vibration and the deviation relative to the advancing direction when the motor operates at high speed are restrained.

摘要翻译： 提供了一种电动机控制系统和电动机控制方法，其可以通过在运行期间通过抑制振动和相对于前进方向的偏差来缩短建立时间。 此外，根据本发明，可以使电动机以理想轨道进行操作，并且由于可以始终监视当前位置，所以容易使多个轴同步操作。 电动机控制系统设置有从相对于前进方向的振动具有显着影响的加加数据产生指令波形的单元，以及根据偏差量执行再生未来指令波形的实时实际位置控制的单元， 同时总是进行加加速度限制，从而抑制当电动机高速运转时相对于前进方向的振动和偏差。

公开(公告)号：US20120212171A1

公开(公告)日：2012-08-23

申请号：US13044000

申请日：2011-03-09

申请人： Mitsuaki TATE ,  Yasushi Ishii ,  Masamichi Kihara

发明人： Mitsuaki TATE ,  Yasushi Ishii ,  Masamichi Kihara

IPC分类号： G05B19/416

CPC分类号： G05B19/351 ,  G05B11/26 ,  G05B2219/41217 ,  H02P23/20

摘要： There is provided a motor control system and motor control method which can shorten settling time by restraining vibration and deviation relative to an advancing direction during operation. Moreover, according to the present invention, it is possible to cause a motor to be operated with an ideal track and, since it is possible to always monitor a present position, it is made easy to cause a plurality of axes to be synchronously operated. The motor control system is provided with a unit generating command waveforms from a jerk data which has significant effects on the vibration relative to the advancing direction, and a unit performing a real time real position control of regenerating future command waveforms according to a deviation amount, while always performing jerk-limit, whereby the vibration and the deviation relative to the advancing direction when the motor operates at high speed are restrained.

摘要翻译： 提供了一种电动机控制系统和电动机控制方法，其可以通过在运行期间通过抑制振动和相对于前进方向的偏差来缩短建立时间。 此外，根据本发明，可以使电动机以理想轨道进行操作，并且由于可以始终监视当前位置，所以容易使多个轴同步操作。 电动机控制系统设置有从相对于前进方向的振动具有显着影响的加加数据产生指令波形的单元，以及根据偏差量执行再生未来指令波形的实时实际位置控制的单元， 同时总是进行加加速度限制，从而抑制当电动机高速运转时相对于前进方向的振动和偏差。

公开(公告)号：US08373216B2

公开(公告)日：2013-02-12

申请号：US12913759

申请日：2010-10-27

申请人： Hiraku Chakihara ,  Yasushi Ishii

发明人： Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/94

CPC分类号： H01L27/11575 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

摘要： Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

摘要翻译： 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

公开(公告)号：US20120313160A1

公开(公告)日：2012-12-13

申请号：US13591035

申请日：2012-08-21

申请人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

发明人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

IPC分类号： H01L29/792

CPC分类号： H01L29/7885 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328

摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.

摘要翻译： 提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。 存储栅电极的高度低于控制栅电极的高度。 在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。 存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。 该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。 本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。

公开(公告)号：US08084800B2

公开(公告)日：2011-12-27

申请号：US12239807

申请日：2008-09-28

申请人： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

发明人： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

摘要： In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

摘要翻译： 关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。 电容器元件形成在半导体衬底上形成的元件隔离区域中。 电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。 基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。 形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。 此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。

公开(公告)号：US20110095348A1

公开(公告)日：2011-04-28

申请号：US12913759

申请日：2010-10-27

申请人： Hiraku CHAKIHARA ,  Yasushi Ishii

发明人： Hiraku CHAKIHARA ,  Yasushi Ishii

IPC分类号： H01L29/94 ,  H01L21/336 ,  H01L27/088

CPC分类号： H01L27/11575 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

摘要： Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

摘要翻译： 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

公开(公告)号：US07863670B2

公开(公告)日：2011-01-04

申请号：US12490147

申请日：2009-06-23

申请人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

发明人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/6653

摘要： In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

摘要翻译： 在包括具有控制栅极和存储器栅极的分离栅极型存储单元，低耐压MISFET和高耐压MISFET的半导体器件中，抑制了存储单元的阈值电压的变化。 控制栅极的栅极绝缘膜比高耐压MISFET的栅极绝缘膜薄，控制栅极比低耐压MISFET的栅电极14厚，存储栅的厚度比相对于 存储器栅极的栅极长度大于1.控制栅极和栅电极15形成为包括电极材料膜8A和电极材料层8B的多层结构，并且栅电极14是形成的单层结构 同时作为控制栅极的电极材料膜8A。

公开(公告)号：US07767522B2

公开(公告)日：2010-08-03

申请号：US11715348

申请日：2007-03-08

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

IPC分类号： H01L21/336

CPC分类号： H01L29/7885 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328

摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.

摘要翻译： 提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。 存储栅电极的高度低于控制栅电极的高度。 在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。 存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。 该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。 本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。

公开(公告)号：US07745288B2

公开(公告)日：2010-06-29

申请号：US11717053

申请日：2007-03-13

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US07719052B2

公开(公告)日：2010-05-18

申请号：US12020393

申请日：2008-01-25

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。