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公开(公告)号：US06512413B2
公开(公告)日：2003-01-28
申请号：US10154852
申请日：2002-05-28
申请人： Mitsuhiko Okutsu , Shoji Sato
发明人： Mitsuhiko Okutsu , Shoji Sato
IPC分类号： G05F324
CPC分类号： H02M3/07
摘要： A voltage boost circuit operates by applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and, in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of said booster capacitance, a pulse width of the one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.
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公开(公告)号：US06433623B1
公开(公告)日：2002-08-13
申请号：US09421236
申请日：1999-10-20
申请人： Mitsuhiko Okutsu , Shoji Sato
发明人： Mitsuhiko Okutsu , Shoji Sato
IPC分类号： G05F324
CPC分类号： H02M3/07
摘要： A voltage boost circuit operates by: applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of the booster capacitance, a pulse width of said one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.
摘要翻译： 升压电路通过以下方式工作：在放电期间对增压电容的两端施加电源电压; 并且在随着放电期间的充电期间，通过响应于施加单次脉冲而接通开关电路，向所述升压电容的一个端子施加电源电压，将另一个施加接地电位 其中，在所述升压电容的充电期间，根据所述电源电压的大小来调整所述单触发脉冲的脉冲宽度。
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公开(公告)号：US20060238216A1
公开(公告)日：2006-10-26
申请号：US11446219
申请日：2006-06-05
IPC分类号： H03K19/195
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
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公开(公告)号：US07061825B2
公开(公告)日：2006-06-13
申请号：US10867013
申请日：2004-06-15
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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公开(公告)号：US20050047265A1
公开(公告)日：2005-03-03
申请号：US10867013
申请日：2004-06-15
IPC分类号： G06F1/12 , G06F1/04 , G06F1/08 , G11C7/22 , G11C8/00 , H03K3/03 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/08
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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公开(公告)号：US07193929B2
公开(公告)日：2007-03-20
申请号：US11446219
申请日：2006-06-05
IPC分类号： G11C8/18
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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公开(公告)号：US07126872B2
公开(公告)日：2006-10-24
申请号：US10961134
申请日：2004-10-12
申请人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
发明人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
摘要： In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.
摘要翻译： 考虑到在输入电源时控制过冲，而不增加安装在半导体集成电路上的电压产生电路中的芯片占用的面积，内部电压产生电路包括电压产生电路，用于从第一 从外部提供的电压，以及用于产生对应于第二电压的第三电压的输出缓冲器。 第三电压用作内部电路的工作电源。 此外，还提供了用于使得第二电压的输出节点能够导通到预定电位的第一开关和用于响应于第一电压的输入而使第一开关接通预定时段的控制电路。 输出缓冲器的输出端子不被钳位，而前一级的电压产生电路的输出被钳位到预定电压。 与输出缓冲器的输出晶体管相比，用于钳位电压的第一开关的晶体管的尺寸可以显着减小。 因此，芯片所占据的面积不会扩大。
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公开(公告)号：US4967100A
公开(公告)日：1990-10-30
申请号：US286861
申请日：1988-12-20
IPC分类号： G09G3/22 , G09G3/30 , H03K17/567 , H03K17/62 , H03K17/66
CPC分类号： H03K17/667 , H03K17/567 , H03K17/6285
摘要： A capacitive load driving apparatus which has a plurality of first switching elements connected between a plurality of parallel loads and a first power source terminal for switching currents which charge the loads. There is furthermore provided a plurality of bipolar transistors connected between connecting points (of the first switching elements and the loads) and a second power source terminal for discharging charges stored in the loads and a plurality of second switching elements connected between a third power source terminal and bases of the bipolar transistor, respectively, for switching base currents supplied from the third power source terminal to the bipolar transistors. In addition, the capacitive load driving apparatus has a logic circuit connected to an input terminal for providing driving signals which turn off selectively one or all of the second switching elements in accordance with a signal from the input terminal, and it has a resistor connected between the third power source terminal and the second switching elements.
摘要翻译： 一种容性负载驱动装置，其具有连接在多个并联负载之间的多个第一开关元件和用于切换对负载充电的电流的第一电源端子。 此外还提供了连接在第一开关元件和负载的连接点之间的多个双极晶体管和用于放电存储在负载中的电荷的第二电源端子以及连接在第三电源端子之间的多个第二开关元件 和双极晶体管的基极，用于将从第三电源端子提供的基极电流切换到双极晶体管。 此外，电容性负载驱动装置具有连接到输入端子的逻辑电路，用于提供根据来自输入端子的信号选择性地关闭第二开关元件中的一个或全部的驱动信号，并且其具有连接在 第三电源端子和第二开关元件。
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公开(公告)号：US4733106A
公开(公告)日：1988-03-22
申请号：US718283
申请日：1985-04-01
申请人： Mitsuhiko Okutsu , Tatsuo Shimura , Tadaaki Kariya
发明人： Mitsuhiko Okutsu , Tatsuo Shimura , Tadaaki Kariya
IPC分类号： H03K17/73 , H02N2/00 , H03K17/04 , H03K17/732 , H03K3/26
CPC分类号： H03K17/0403 , H03K17/732
摘要： A device for driving a capacitive load, comprising a first switching element responsive to an external control signal for selectively conducting a charge current therethrough to the load, a second switching element responsive to the external control signal for conducting a discharge current from the load and a generator for generating from the discharge current a cutoff signal to be applied to the first switching element to ensure turn-off of the latter.
摘要翻译： 一种用于驱动电容性负载的装置，包括响应于外部控制信号的第一开关元件，用于选择性地将充电电流传导到负载;第二开关元件，响应于外部控制信号，用于从负载传导放电电流;以及 发生器，用于从放电电流产生要施加到第一开关元件的截止信号，以确保后者的关断。
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公开(公告)号：US20080309383A1
公开(公告)日：2008-12-18
申请号：US12107069
申请日：2008-04-21
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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