公开(公告)号：US5206830A

公开(公告)日：1993-04-27

申请号：US733126

申请日：1991-07-19

申请人： Mitsuo Isobe ,  Hisashi Ueno

发明人： Mitsuo Isobe ,  Hisashi Ueno

IPC分类号： G11C7/00 ,  G11C11/403 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

摘要翻译： 用于伪静态随机存取存储器的刷新控制电路包括刷新控制信号输出电路，用于输出刷新控制信号以完成伪静态随机存取存储器的刷新控制，并且包括延迟电路。 来自诸如MPU的控制装置的第一芯片使能信号被延迟电路延迟并作为PSRAM的第二芯片使能信号输出。 当第一芯片使能信号电平从选择电平变化到非选择电平时，刷新控制信号电平变为非刷新电平。 该状态保持预定的时间。 在第二芯片使能信号从选择电平变化到非选择电平之后，刷新控制信号从非刷新电平返回到刷新电平。 因此，PSRAM在非选择状态期间进入刷新状态，并被刷新。 这种刷新操作必须在访问PSRAM之后执行。

公开(公告)号：US4939695A

公开(公告)日：1990-07-03

申请号：US268927

申请日：1988-11-09

申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Kazutaka Nogami ,  Hisashi Ueno

发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Kazutaka Nogami ,  Hisashi Ueno

IPC分类号： G11C11/403 ,  G11C11/406

CPC分类号： G11C11/406

摘要： A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

公开(公告)号：US5027327A

公开(公告)日：1991-06-25

申请号：US339661

申请日：1989-04-18

申请人： Makiji Kobayashi ,  Mitsuo Isobe ,  Tatsuya Inatsuki ,  Hisashi Ueno

发明人： Makiji Kobayashi ,  Mitsuo Isobe ,  Tatsuya Inatsuki ,  Hisashi Ueno

IPC分类号： G11C11/403 ,  G11C11/406 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/406

摘要： A semiconductor memory having dynamic memory cells includes a determining circuit for determining whether or not it is necessary to refresh the dynamic memory cells, and only when it is necessary, outputting a refresh execution signal in response to a refresh request signal from an external circuit, and a circuit for executing a refresh operation in response to the refresh execution signal. Even if the refresh request signal is supplied, a refresh operation is not executed unless the determining circuit determines that the refresh operation is necessary, thus dispensing with unnecessary refresh operations. Preferably, the determining circuit includes a timer which outputs a signal at every predetermined period. Only when the signal is output from the timer, is the refresh request signal from an external circuit accepted and the refresh execution signal output.

公开(公告)号：US5075886A

公开(公告)日：1991-12-24

申请号：US375856

申请日：1989-07-06

申请人： Mitsuo Isobe ,  Hisashi Ueno

发明人： Mitsuo Isobe ,  Hisashi Ueno

IPC分类号： G11C7/00 ,  G11C11/403 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level also changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

摘要翻译： 用于伪静态随机存取存储器的刷新控制电路包括刷新控制信号输出电路，用于输出刷新控制信号以完成伪静态随机存取存储器的刷新控制，并且包括延迟电路。 来自诸如MPU的控制装置的第一芯片使能信号被延迟电路延迟并作为PSRAM的第二芯片使能信号输出。 当第一芯片使能信号电平从选择电平变化到非选择电平时，刷新控制信号电平也变为非刷新电平。 该状态保持预定的时间。 在第二芯片使能信号从选择电平变化到非选择电平之后，刷新控制信号从非刷新电平返回到刷新电平。 因此，PSRAM在非选择状态期间进入刷新状态，并被刷新。 这种刷新操作必须在访问PSRAM之后执行。

公开(公告)号：US5414330A

公开(公告)日：1995-05-09

申请号：US20567

申请日：1993-02-22

申请人： Susumu Tsujihara ,  Mitsuo Isobe ,  Hiroyosi Shimosaka ,  Hiroshi Taniguchi

发明人： Susumu Tsujihara ,  Mitsuo Isobe ,  Hiroyosi Shimosaka ,  Hiroshi Taniguchi

IPC分类号： H04N3/22 ,  H04N3/233 ,  H04N9/24 ,  H04N9/28 ,  G09G1/04 ,  H01J29/10 ,  H01J31/26

CPC分类号： H04N9/24 ,  H04N3/22 ,  H04N3/2335 ,  H04N9/28

摘要： A cathode ray tube control apparatus includes phosphor display screen, three electron guns for emitting R, G, B electron beams to the display screen, a shadow mask placed between the electron guns and the display screen, and index phosphors deposited on the shadow mask and having at least two line elements diagonal to a horizontal scanning direction of the electron beam for generating a signal according to the electron beam scan. Further provided are detector for detecting beam crossing points over the index phosphor, and correction circuit for correcting the deflection of the electron beam based on the detected beam crossing points.

摘要翻译： 阴极射线管控制装置包括荧光显示屏，用于向显示屏发射R，G，B电子束的三个电子枪，放置在电子枪和显示屏之间的荫罩，以及沉积在荫罩上的折射荧光体， 具有与电子束的水平扫描方向对角的至少两个线元件，用于根据电子束扫描产生信号。 还提供了用于检测指示荧光体上的光束交叉点的检测器，以及用于基于检测到的光束交叉点校正电子束的偏转的校正电路。

公开(公告)号：US5003389A

公开(公告)日：1991-03-26

申请号：US437688

申请日：1989-11-17

申请人： Mitsuo Isobe ,  Masanori Hamada ,  Katsumi Morita ,  Yuichi Ninomiya

发明人： Mitsuo Isobe ,  Masanori Hamada ,  Katsumi Morita ,  Yuichi Ninomiya

IPC分类号： H04N19/102 ,  H04N5/14 ,  H04N5/46 ,  H04N7/015 ,  H04N7/24 ,  H04N11/00 ,  H04N11/24 ,  H04N19/00 ,  H04N19/132 ,  H04N19/137 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/59 ,  H04N19/80

CPC分类号： H04N5/144 ,  H04N5/46 ,  H04N7/0152 ,  H04N7/24

摘要： An image signal processing apparatus is provided which is applicable to a motion adaptive Y/C separation of an NTSC signal and a time-domain/spatial interpolation of a high definition television signal band-compressed by sub-Nyquist sub-sampling. The apparatus includes a still image processing circuit having frame memories, a motion image processing circuit having a line memory, a mixing circuit for mixing outputs of these processing circuits, a circuit for detecting image motion of an input image signal and applying a resultant control signal to the mixing circuit, and a signal mode control circuit for selectively adapting the image processing circuits for the processing of the NTSC signal or the high definition television signal. The motion detecting circuit includes a narrow band detecting circuit for producing a one-frame interval difference signal of a signal spectrum of a pure low frequency component from the NTSC signal or the high definition television signal respectively, a wide band detecting circuit for a two-frame interval difference signal and a composition circuit for composing outputs of these detecting circuits. The still image processing circuit, motion image processing circuit and mixing circuit are adapted to operate for the Y/C separation with the NTSC signal and for the interpolation of the high definition television signal, respectively.

公开(公告)号：US4963969A

公开(公告)日：1990-10-16

申请号：US314087

申请日：1989-02-23

申请人： Hiromu Kitaura ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

发明人： Hiromu Kitaura ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

IPC分类号： H04N5/04 ,  H04N5/52 ,  H04N7/015

CPC分类号： H04N5/52

摘要： Disclosed is an automatic gain control device which comprises: a first amplitude detection circuit for detecting an average amplitude value of a television video signal, a peak amplitude value of the same television video signal, or a value obtained by mixing the average amplitude value and the peak amplitude value with a predetermined mixing ratio; a second amplitude detection circuit for detecting an amplitude value of a vertical or horizontal synchronizing signal in the television video signal; an amplitude control circuit for controlling an amplitude of an input television video signal; a synchronization circuit for detecting a vertical synchronizing signal and a horizontal synchronizing signal in the television video signal so as to generate various pulses including a clock pulse synchronized with the input television video signal by controlling an oscillation frequency of an oscillation circuit; and a synchronization phase lock detection circuit for detecting whether the synchronization circuit has been pulled into synchronism with the input television video signal, so that the amplitude control circuit is controlled by an output of the second amplitude detection circuit when synchronization phase-lock is established while controlled by an output of the first amplitude detection circuit when the synchronization phase-lock comes out.

摘要翻译： 公开了一种自动增益控制装置，包括：第一幅度检测电路，用于检测电视视频信号的平均振幅值，相同电视视频信号的峰值振幅值，或通过混合平均振幅值和 具有预定混合比的峰值振幅值; 第二振幅检测电路，用于检测电视视频信号中的垂直或水平同步信号的振幅值; 幅度控制电路，用于控制输入电视视频信号的幅度; 用于检测电视视频信号中的垂直同步信号和水平同步信号的同步电路，以通过控制振荡电路的振荡频率产生包括与输入电视视频信号同步的时钟脉冲的各种脉冲; 以及同步锁相检测电路，用于检测同步电路是否已被拉入与输入的电视视频信号同步，使得当建立同步锁相时，幅度控制电路由第二幅度检测电路的输出控制，而 当同步锁相出来时由第一幅度检测电路的输出控制。

公开(公告)号：US4950926A

公开(公告)日：1990-08-21

申请号：US261066

申请日：1988-10-24

申请人： Mitsuo Isobe ,  Shinich Nakauchida

发明人： Mitsuo Isobe ,  Shinich Nakauchida

IPC分类号： G11C11/41 ,  G11C11/409 ,  H01L27/10 ,  H03K19/00

CPC分类号： H03K19/0013

摘要： A control signal output circuit for outputting a control signal in response to first and second input signals and a power source voltage, comprises an inverter which inverts one of the first and second input signals and outputs an inverted signal. The control signal output circuit further comprises a logic circuit which outputs a control signal in response to the inverted signal and the other of the first and second input signals. A switch is further provided to disconnect the inverter from the power source voltage in response to the other of the first and second input signals.

摘要翻译： 用于响应于第一和第二输入信号和电源电压而输出控制信号的控制信号输出电路包括反相器，其将第一和第二输入信号之一反相并输出反相信号。 控制信号输出电路还包括逻辑电路，其响应于反相信号和第一和第二输入信号中的另一个输出控制信号。 进一步提供开关以响应于第一和第二输入信号中的另一个而断开逆变器与电源电压的连接。

公开(公告)号：US4744063A

公开(公告)日：1988-05-10

申请号：US613614

申请日：1984-05-24

申请人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

发明人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/418 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/18

摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

摘要翻译： 静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。 当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。 该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

公开(公告)号：US5808699A

公开(公告)日：1998-09-15

申请号：US688305

申请日：1996-07-20

申请人： Susumu Tsujihara ,  Ikunori Inoue ,  Yoshio Seki ,  Mitsuo Isobe

发明人： Susumu Tsujihara ,  Ikunori Inoue ,  Yoshio Seki ,  Mitsuo Isobe

IPC分类号： H04N5/18 ,  H04N5/202 ,  H04N5/57

CPC分类号： H04N5/18 ,  H04N5/202 ,  H04N5/57

摘要： A visual image signal processing apparatus includes: an overlaying unit for overlaying a brightness reference signal at a predetermined position in a fly-back period of an input visual image signal; a first clamping unit for clamping an output from the overlaying unit at a predetermined clamping voltage; a detecting unit for applying an output from the first clamping unit to a driving electrode of a cathode ray tube and for detecting a beam current flowing based on the brightness reference signal overlaid in the input visual image signal; and a second clamping unit for controlling the predetermined clamp voltage based on the beam current detected by the detecting unit.

摘要翻译： 视觉图像信号处理装置包括：重叠单元，用于在输入视觉信号的回扫周期中将亮度参考信号叠加在预定位置; 第一夹紧单元，用于以预定的钳位电压钳位来自覆盖单元的输出; 检测单元，用于将来自第一夹持单元的输出施加到阴极射线管的驱动电极，并用于基于重叠在输入视觉信号中的亮度参考信号来检测流过的束流; 以及第二夹持单元，用于基于由检测单元检测到的束电流来控制预定的钳位电压。