公开(公告)号：US20110207263A1

公开(公告)日：2011-08-25

申请号：US13101454

申请日：2011-05-05

Applicant: Mitsuru WATANABE ,  Tetsuya FUKUI

Inventor： Mitsuru WATANABE ,  Tetsuya FUKUI

IPC: H01L21/78

CPC classification number: H01L24/34 ,  H01L23/49562 ,  H01L24/37 ,  H01L2224/32245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: The present invention relates to a method of manufacturing a semiconductor device including (1) forming a laminated structure on a major surface of a semiconductor substrate, the laminated structure comprising at least a first metal layer that forms a Schottky junction with the semiconductor substrate, a second metal layer primarily composed of aluminum, and a third metal layer primarily composed of molybdenum or titanium, (2) patterning the laminated structure into a predetermined configuration, (3) forming a solder bonding metal layer comprising at least nickel, ion or cobalt on the major surface of the semiconductor substrate having the patterned laminated structure formed thereon, (4) patterning the solder bonding metal layer into a pattern configuration identical to that of the laminated structure, (5) cutting the semiconductor substrate on which the laminated structure and the solder bonding metal layer are patterned to form a plurality of semiconductor chips, and (6) bonding the semiconductor chip to a first frame using at least one solder layer formed on the solder bonding metal layer on the major surface of the semiconductor substrate, and bonding a rear face of the semiconductor chip to a second frame.

Abstract translation: 本发明涉及一种制造半导体器件的方法，该半导体器件包括：（1）在半导体衬底的主表面上形成叠层结构，所述层压结构至少包括与半导体衬底形成肖特基结的第一金属层， 主要由铝构成的第二金属层和主要由钼或钛构成的第三金属层，（2）将层压结构图案化为规定的构造，（3）形成至少包含镍，离子或钴的焊料接合金属层， （4）将焊料接合金属层图案化为与层叠结构相同的图案构造，（5）切割其上层叠结构和层叠结构的半导体基板，其中， 图案化焊接金属层以形成多个半导体芯片，（6）将焊接接合金属层接合 使用在所述半导体衬底的主表面上的所述焊料接合金属层上形成的至少一个焊料层，将所述半导体芯片的后表面接合到第二框架的第一框架。