SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT
    1.
    发明申请
    SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT 有权
    用于集成电路防止篡改的系统

    公开(公告)号:US20140353849A1

    公开(公告)日:2014-12-04

    申请号:US13905150

    申请日:2013-05-30

    IPC分类号: H01L23/00

    摘要: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

    摘要翻译: 用于产生表示篡改集成电路(IC)的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对 。 线网放置在与电路预定距离的位置。 篡改检测模块生成并提供串行比特流到线对,用于通过外部探针检测金属丝网中的突破。

    System for preventing tampering with integrated circuit
    2.
    发明授权
    System for preventing tampering with integrated circuit 有权
    防止篡改集成电路的系统

    公开(公告)号:US08896086B1

    公开(公告)日:2014-11-25

    申请号:US13905150

    申请日:2013-05-30

    IPC分类号: H01L23/02 H01L23/00

    摘要: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

    摘要翻译: 用于产生表示篡改集成电路(IC)的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对 。 线网放置在与电路预定距离的位置。 篡改检测模块生成并提供串行比特流到线对,用于通过外部探针检测金属丝网中的突破。

    Tamper detector for secure module
    3.
    发明授权
    Tamper detector for secure module 有权
    防拆检测器用于安全模块

    公开(公告)号:US08689357B2

    公开(公告)日:2014-04-01

    申请号:US13475947

    申请日:2012-05-19

    IPC分类号: G06F21/00

    CPC分类号: G06F21/72 G06F21/755

    摘要: A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.

    摘要翻译: 篡改检测器具有用于连接到篡改检测电路的端部的输入和输出引脚和由时钟信号定时的对应的一组线性反馈移位寄存器(LFSR),用于产生作为种子值的函数的伪随机编码检测信号,以及 由反馈抽头定义的生成多项式。 比较器将从检测电路接收的信号与编码的检测信号进行比较。 复用器将选择性地从LFSR向编码的检测信号提供给输出引脚和比较器。 控制器改变伪随机编码检测信号的不同周期值的种子值。 控制器还控制生成多项式和针对伪随机编码检测信号的不同周期值的时钟信号的频率。

    REAL-TIME CLOCK (RTC) MODIFICATION DETECTION SYSTEM
    4.
    发明申请
    REAL-TIME CLOCK (RTC) MODIFICATION DETECTION SYSTEM 审中-公开
    实时时钟(RTC)修改检测系统

    公开(公告)号:US20150186676A1

    公开(公告)日:2015-07-02

    申请号:US14145991

    申请日:2014-01-01

    IPC分类号: G06F21/64

    CPC分类号: G06F21/725

    摘要: A system for securing a real-time clock (RTC) of an electronic device includes a RTC counter that counts clock pulses of a RTC signal generated by a crystal oscillator, and a reference-time register that periodically stores a reference time value generated by a network-clock generator. A hash-value generator uses a predefined hash algorithm to generate first and second hash values based on the reference time value and the count of the RTC counter, respectively, at predetermined time intervals. A comparator compares the first and second hash values and generates a trigger signal when there is a mismatch.

    摘要翻译: 用于保护电子设备的实时时钟(RTC)的系统包括对由晶体振荡器产生的RTC信号的时钟脉冲进行计数的RTC计数器和周期性地存储由 网络时钟发生器。 散列值生成器使用预定义的散列算法,以预定的时间间隔分别基于参考时间值和RTC计数器的计数来产生第一和第二散列值。 比较器比较第一和第二散列值,并且当存在不匹配时产生触发信号。

    System for compensating for variations in clock signal frequency
    5.
    发明授权
    System for compensating for variations in clock signal frequency 有权
    用于补偿时钟信号频率变化的系统

    公开(公告)号:US08643410B1

    公开(公告)日:2014-02-04

    申请号:US13602199

    申请日:2012-09-02

    IPC分类号: H03K9/08

    CPC分类号: G04F10/04 H03L7/00

    摘要: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

    摘要翻译: 用于补偿具有第一频率的输入时钟信号的频率变化的系统包括接收输入时钟信号的粗计数器,对输入时钟信号的预定数量的时钟脉冲进行计数,并产生具有 第二个频率。 第一补偿模块基于粗略的补偿值调整输入时钟信号的时钟脉冲。 残余周期调整模块对粗补偿时钟信号的每个时钟脉冲累积精细补偿值。 精细计数器以精细时钟信号的第三频率工作,基于累积的精细补偿值接收经调整的延迟值,对粗略补偿时钟信号的每个时钟脉冲中的精细时钟脉冲数进行计数,并产生精细补偿 时钟信号具有第二频率。

    Apparatus and method for decoupling asynchronous clock domains
    6.
    发明授权
    Apparatus and method for decoupling asynchronous clock domains 有权
    用于解耦异步时钟域的装置和方法

    公开(公告)号:US08443224B2

    公开(公告)日:2013-05-14

    申请号:US12912780

    申请日:2010-10-27

    IPC分类号: G06F1/12 G06F1/04 G06F5/06

    CPC分类号: G06F1/12

    摘要: A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.

    摘要翻译: 用于在数字电子电路内的异步时钟域之间同步信号的电路和方法解耦异步时钟。 较慢时钟的定时用于防止读取和写入计数器,以便当计数器不切换时,来自快速时钟域的写入信号可以直接用于较慢时钟域。 该功能消除了对快速时钟采样和保持数据的需求,这将需要消耗额外的功率并需要额外的电路面积。

    Method for low power boot for microcontroller
    7.
    发明授权
    Method for low power boot for microcontroller 有权
    微控制器低功耗引导方法

    公开(公告)号:US09152430B2

    公开(公告)日:2015-10-06

    申请号:US13910092

    申请日:2013-06-04

    摘要: A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

    摘要翻译: 微控制器包括具有内部参考时钟的时钟发生器,建立操作模式的系统模式控制器,具有内部时钟和非易失性选项寄存器的闪存,以及耦合到系统模式控制器的引导模式选择逻辑电路, 闪存。 逻辑电路输出指示微控制器以非常低功率运行(VLPR)模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前,以及在RUN模式下闪存初始化之前,会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。

    METHOD FOR LOW POWER BOOT FOR MICROCONTROLLER
    8.
    发明申请
    METHOD FOR LOW POWER BOOT FOR MICROCONTROLLER 有权
    微电脑低功耗引擎的方法

    公开(公告)号:US20140359264A1

    公开(公告)日:2014-12-04

    申请号:US13910092

    申请日:2013-06-04

    IPC分类号: G06F9/44

    摘要: A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

    摘要翻译: 微控制器包括具有内部参考时钟的时钟发生器,建立操作模式的系统模式控制器,具有内部时钟和非易失性选项寄存器的闪存,以及耦合到系统模式控制器的引导模式选择逻辑电路, 闪存。 逻辑电路输出指示微控制器以非常低功率运行(VLPR)模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前,以及在RUN模式下闪存初始化之前,会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。

    TAMPER DETECTOR FOR SECURE MODULE
    9.
    发明申请
    TAMPER DETECTOR FOR SECURE MODULE 有权
    用于安全模块的夯实检测器

    公开(公告)号:US20130312122A1

    公开(公告)日:2013-11-21

    申请号:US13475947

    申请日:2012-05-19

    IPC分类号: G06F21/02

    CPC分类号: G06F21/72 G06F21/755

    摘要: A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.

    摘要翻译: 篡改检测器具有用于连接到篡改检测电路的端部的输入和输出引脚和由时钟信号定时的对应的一组线性反馈移位寄存器(LFSR),用于产生作为种子值的函数的伪随机编码检测信号,以及 由反馈抽头定义的生成多项式。 比较器将从检测电路接收的信号与编码的检测信号进行比较。 复用器将选择性地从LFSR向编码的检测信号提供给输出引脚和比较器。 控制器改变伪随机编码检测信号的不同周期值的种子值。 控制器还控制生成多项式和针对伪随机编码检测信号的不同周期值的时钟信号的频率。

    APPARATUS AND METHOD FOR DECOUPLING ASYNCHRONOUS CLOCK DOMAINS
    10.
    发明申请
    APPARATUS AND METHOD FOR DECOUPLING ASYNCHRONOUS CLOCK DOMAINS 有权
    用于解除异步时钟域的装置和方法

    公开(公告)号:US20120110364A1

    公开(公告)日:2012-05-03

    申请号:US12912780

    申请日:2010-10-27

    IPC分类号: G06F1/12

    CPC分类号: G06F1/12

    摘要: A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.

    摘要翻译: 用于在数字电子电路内的异步时钟域之间同步信号的电路和方法解耦异步时钟。 较慢时钟的定时用于防止读取和写入计数器,以便当计数器不切换时,来自快速时钟域的写入信号可以直接用于较慢时钟域。 该功能消除了对快速时钟采样和保持数据的需求,这将需要消耗额外的功率并需要额外的电路面积。