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公开(公告)号：US09152430B2
公开(公告)日：2015-10-06
申请号：US13910092
申请日：2013-06-04
CPC分类号： G06F9/4406 , G06F1/24 , G06F1/30 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F9/4401 , G06F11/1417
摘要： A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.
摘要翻译： 微控制器包括具有内部参考时钟的时钟发生器，建立操作模式的系统模式控制器，具有内部时钟和非易失性选项寄存器的闪存，以及耦合到系统模式控制器的引导模式选择逻辑电路， 闪存。 逻辑电路输出指示微控制器以非常低功率运行（VLPR）模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前，以及在RUN模式下闪存初始化之前，会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。
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公开(公告)号：US20140359264A1
公开(公告)日：2014-12-04
申请号：US13910092
申请日：2013-06-04
IPC分类号： G06F9/44
CPC分类号： G06F9/4406 , G06F1/24 , G06F1/30 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F9/4401 , G06F11/1417
摘要： A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.
摘要翻译： 微控制器包括具有内部参考时钟的时钟发生器，建立操作模式的系统模式控制器，具有内部时钟和非易失性选项寄存器的闪存，以及耦合到系统模式控制器的引导模式选择逻辑电路， 闪存。 逻辑电路输出指示微控制器以非常低功率运行（VLPR）模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前，以及在RUN模式下闪存初始化之前，会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。
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公开(公告)号：US08643410B1
公开(公告)日：2014-02-04
申请号：US13602199
申请日：2012-09-02
IPC分类号： H03K9/08
摘要： A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.
摘要翻译： 用于补偿具有第一频率的输入时钟信号的频率变化的系统包括接收输入时钟信号的粗计数器，对输入时钟信号的预定数量的时钟脉冲进行计数，并产生具有 第二个频率。 第一补偿模块基于粗略的补偿值调整输入时钟信号的时钟脉冲。 残余周期调整模块对粗补偿时钟信号的每个时钟脉冲累积精细补偿值。 精细计数器以精细时钟信号的第三频率工作，基于累积的精细补偿值接收经调整的延迟值，对粗略补偿时钟信号的每个时钟脉冲中的精细时钟脉冲数进行计数，并产生精细补偿 时钟信号具有第二频率。
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4.发明申请CLOCK CIRCUIT FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL, ELECTRONIC DEVICE WITH A CLOCK CIRCUIT AND METHOD FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL 有权用于提供具有时钟信号的电子设备的时钟电路，具有时钟电路的电子设备和用于提供具有时钟信号的电子设备的方法公开(公告)号：US20130113527A1
公开(公告)日：2013-05-09
申请号：US13810523
申请日：2010-07-20
申请人： Martin Mienkina
发明人： Martin Mienkina
IPC分类号： G06F1/08
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.
摘要翻译： 本发明涉及一种用于向电子设备提供具有可调时钟频率的时钟信号的时钟电路。 时钟电路适于接收关于电子设备的上下文级别的信息，并且根据上下文级别来动态地控制时钟信号的时钟频率。 基于上下文级别的时钟电路输出频率的动态控制实现了电子设备的自动功率对性能的控制。 本发明还涉及一种电子设备，包括适于设置电子设备操作的上下文级别和时钟电路的上下文设置单元。 此外，本发明涉及一种向电子设备提供具有可调时钟频率的时钟信号的方法，其中时钟电路接收关于电子设备的上下文级别的信息; 并且其中所述时钟电路根据所述上下文级别来动态地控制所述时钟信号的时钟频率。
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5.发明授权公开(公告)号：US09465481B2
公开(公告)日：2016-10-11
申请号：US14417648
申请日：2012-08-03
申请人： Peter Moravcik , Martin Mienkina
发明人： Peter Moravcik , Martin Mienkina
CPC分类号： G06F3/0418 , G06F3/044
摘要： A method and apparatus for performing touch detection within a touch sensing application is described. Touch sensor signal data is received, a first filtering of the received touch sensor signal data to create a first filtered data signal is performed, a second filtering of the received touch sensor signal data to create a second filtered data signal is also performed, a difference between the first and second filtered data signals to determine a delta value is calculated, and an occurrence of a touch based at least partly on the determined delta value is determined.
摘要翻译： 描述了用于在触摸感测应用内执行触摸检测的方法和装置。 接收触摸传感器信号数据，对接收到的触摸传感器信号数据进行第一次滤波以产生第一滤波数据信号，对接收的触摸传感器信号数据进行第二次滤波以产生第二滤波数据信号， 在第一和第二滤波数据信号之间，以确定增量值被计算，并且确定至少部分地基于确定的增量值的触摸的出现。
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公开(公告)号：US10481795B2
公开(公告)日：2019-11-19
申请号：US14708969
申请日：2015-05-11
摘要： A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.
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公开(公告)号：US10107842B2
公开(公告)日：2018-10-23
申请号：US15025042
申请日：2013-09-27
申请人： Martin Mienkina , Radomir Kozub , Ludek Slosarcik , Lukas Vaculik
发明人： Martin Mienkina , Radomir Kozub , Ludek Slosarcik , Lukas Vaculik
IPC分类号： G01R21/127 , G01R21/133 , G01R22/06 , G01R35/04 , G06F1/26
摘要： There is provided an energy consumption meter device comprising including a processor arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ΔE using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n−1]. The processor will then calculate a relative delay Td′ using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td′ with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.
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公开(公告)号：US09065475B2
公开(公告)日：2015-06-23
申请号：US12302221
申请日：2006-06-01
申请人： Martin Mienkina , Leos Chalupa
发明人： Martin Mienkina , Leos Chalupa
CPC分类号： H03M1/645
摘要： A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.
摘要翻译： Sin-Cos传感器装置包括经由硬件接口可操作地耦合到信号处理逻辑的Sin-Cos传感器。 硬件接口被布置为向信号处理逻辑提供指示精细位置数据的模拟正弦和余弦波形以及指示粗略位置数据的模拟正弦和余弦波形（Phase_A和Phase_B）的二进制对应物。 信号处理逻辑被设置为通过补偿模拟正弦和余弦波形之间的不准确度及其二进制对应来确定Sin-Cos传感器的位置和速度。 以这种方式，完全基于软件的解决方案提供了基于模拟正弦和余弦信号的处理及其Sin-Cos传感器的数字表示的快速，有效和高精度的位置和速度估计。
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公开(公告)号：US08278988B2
公开(公告)日：2012-10-02
申请号：US12997104
申请日：2008-06-27
申请人： Martin Mienkina , Pavel Grasblum
发明人： Martin Mienkina , Pavel Grasblum
IPC分类号： H03H11/26
摘要： A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.
摘要翻译： 一种半导体器件，包括用于产生第一调制波形信号的定时器逻辑和延迟逻辑，其可操作地耦合到定时器逻辑并被布置成在定时器逻辑产生的第一调制波形信号的上升沿提供第一延迟; 并且在由定时器逻辑产生的第一调制波形的下降沿提供第二延迟。 第一调制波形的第一延迟和第二延迟形成第二精细调制波形信号，其包括比第一调制波形信号的频率分辨率更高的频率分辨率。
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10.发明授权公开(公告)号：US09996102B2
公开(公告)日：2018-06-12
申请号：US13810523
申请日：2010-07-20
申请人： Martin Mienkina
发明人： Martin Mienkina
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.
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