公开(公告)号：US20050040895A1

公开(公告)日：2005-02-24

申请号：US10710764

申请日：2004-08-02

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Chih-Yuan Cheng

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Chih-Yuan Cheng

IPC分类号： H03B5/24 ,  H03K3/012 ,  H03K3/03 ,  H03L7/00

CPC分类号： H03K3/0315 ,  H03K3/012

摘要： A low power consumption oscillation circuit and a delay circuit thereof are disclosed. The circuit comprises an enable circuit, an oscillator delay circuit and a feedback control network. The enable circuit is adapted for receiving an enable signal and performing an initial oscillation. The enable circuit outputs an initial oscillation signal according to a feedback control signal. The oscillator delay circuit is coupled to the enable circuit and is adapted for alternately generating a high and a low level oscillation signals according to the initial oscillation signal. The feedback control network is coupled to the oscillator delay circuit and is adapted for integrating the high and the low level oscillation signals to generate a feedback control signal and outputting the feedback control signal to the enable the circuit for activating next oscillation.

摘要翻译： 公开了一种低功耗振荡电路及其延迟电路。 该电路包括使能电路，振荡器延迟电路和反馈控制网络。 使能电路适于接收使能信号并执行初始振荡。 使能电路根据反馈控制信号输出初始振荡信号。 振荡器延迟电路耦合到使能电路，适用于根据初始振荡信号交替产生高电平和低电平的振荡信号。 反馈控制网络耦合到振荡器延迟电路，适用于对高电平和低电平振荡信号进行积分以产生反馈控制信号，并将反馈控制信号输出到启动下一个振荡电路。

公开(公告)号：US07433996B2

公开(公告)日：2008-10-07

申请号：US10880581

申请日：2004-07-01

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

摘要翻译： 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。

公开(公告)号：US07113439B2

公开(公告)日：2006-09-26

申请号：US10829207

申请日：2004-04-22

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

摘要翻译： 一种操作包括以行和列形成的单元阵列的存储器件的方法，所述存储器件包括提供控制信号，激活所述控制信号，所述激活的控制信号包括第一状态和第二状态，响应于所述第一状态和第二状态连续执行访问周期 在一段时间内激活的控制信号的第一状态，并且在该周期的另一部分中响应于激活的控制信号的第二状态连续地执行刷新周期。

公开(公告)号：US07158400B2

公开(公告)日：2007-01-02

申请号：US10711938

申请日：2004-10-14

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Ching-Tang Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Ching-Tang Wu

IPC分类号： G11C11/24

CPC分类号： G11C11/4076 ,  G11C11/404

摘要： A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

摘要翻译： 公开了使用位线和位线条操作动态随机存取存储器（DRAM）的方法。 DRAM通过使用经由开关装置耦合到位线的电荷存储装置来存储数据。 开关器件接通时会发生电压降。 该方法响应于由于电压降而导致的功率电压降低，以第一电压或零电压对电荷存储装置进行编程。 为了访问数据，位线和位线条被充电到电源电压，开关器件导通，并且存储在电荷存储器件中的数据根据​​位线和位线之间的电压差来确定 酒吧。

公开(公告)号：US20060023487A1

公开(公告)日：2006-02-02

申请号：US10711938

申请日：2004-10-14

申请人： Hong-Gee Fang ,  Wen-Chieh Lee

发明人： Hong-Gee Fang ,  Wen-Chieh Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/4076 ,  G11C11/404

摘要： A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

摘要翻译： 公开了使用位线和位线条操作动态随机存取存储器（DRAM）的方法。 DRAM通过使用经由开关装置耦合到位线的电荷存储装置来存储数据。 开关器件接通时会发生电压降。 该方法响应于由于电压降而导致的功率电压降低，以第一电压或零电压对电荷存储装置进行编程。 为了访问数据，位线和位线条被充电到电源电压，开关器件导通，并且存储在电荷存储器件中的数据根据​​位线和位线之间的电压差来确定 酒吧。

公开(公告)号：US20050237836A1

公开(公告)日：2005-10-27

申请号：US10829207

申请日：2004-04-22

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

摘要翻译： 一种操作包括以行和列形成的单元阵列的存储器件的方法，所述存储器件包括提供控制信号，激活所述控制信号，所述激活的控制信号包括第一状态和第二状态，响应于所述第一状态和第二状态连续执行访问周期 在一段时间内激活的控制信号的第一状态，并且在该周期的另一部分中响应于激活的控制信号的第二状态连续地执行刷新周期。

公开(公告)号：US20060004954A1

公开(公告)日：2006-01-05

申请号：US10880581

申请日：2004-07-01

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

摘要翻译： 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。

公开(公告)号：US08338969B2

公开(公告)日：2012-12-25

申请号：US12694564

申请日：2010-01-27

申请人： I-An Chen ,  Wen-Chieh Lee

发明人： I-An Chen ,  Wen-Chieh Lee

IPC分类号： H01L23/48

CPC分类号： G06K19/07732 ,  G06F3/0679

摘要： A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

摘要翻译： 串行高级技术附件（SATA）接口存储设备。 SATA接口存储设备可以与电气设备协同使用，并且包括基板，芯片组，SATA接口和外壳。 衬底具有第一表面，对应于第一表面的第二表面和在第一表面和第二表面之间的多个连接器。 芯片组设置在第一表面上。 SATA接口设置在第二表面上，并且经由一部分连接器电连接到芯片组，使得电气设备可以经由SATA接口电连接到芯片组以访问芯片组。 壳体具有宽度和厚度并且限定用于接收基板，芯片组和SATA接口的接收空间，其中宽度和厚度符合微存储卡标准。

公开(公告)号：US20090104769A1

公开(公告)日：2009-04-23

申请号：US12276419

申请日：2008-11-24

申请人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

发明人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC分类号： H01L21/283

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

摘要翻译： 一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。 所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层 由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

公开(公告)号：US20070223274A1

公开(公告)日：2007-09-27

申请号：US11689760

申请日：2007-03-22

申请人： Wen-Chieh Lee ,  Hsiang-Cheng Ho

发明人： Wen-Chieh Lee ,  Hsiang-Cheng Ho

IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C5/066 ,  G11C5/14 ,  G11C11/005

摘要： A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.

摘要翻译： 提供复杂的存储器芯片。 复合存储器芯片包括第一引脚，第二引脚，电压发生器，闪存和静态随机存取存储器（SRAM）。 第一引脚能够发送第一电压。 第二引脚能够传输低于第一电压的第二电压，以便与第一电压相关联地定义工作电压。 电压发生器根据第一电压产生第三电压，其中第三电压大于第一电压。 闪存和SRAM在工作电压下工作。 闪存根据第三电压擦除数据。