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16 条记录 (耗时 0.031 秒)

    Wafer level packaging cap and fabrication method thereof
    3.
    发明授权
    Wafer level packaging cap and fabrication method thereof 有权
    晶圆级封装盖及其制造方法

    公开(公告)号：US07579685B2

    公开(公告)日：2009-08-25

    申请号：US11339500

    申请日：2006-01-26

    申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    IPC分类号： H01L23/12 ,  H01L23/043

    CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

    摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

    Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor
    5.
    发明申请
    Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor 有权
    具有直接连接到多个晶片的互连电极的封装芯片及其制造方法

    公开(公告)号：US20070013058A1

    公开(公告)日：2007-01-18

    申请号：US11481012

    申请日：2006-07-06

    申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    IPC分类号： H01L23/34

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

    摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

    摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

    Packaging chip having interconnection electrodes directly connected to plural wafers
    6.
    发明授权
    Packaging chip having interconnection electrodes directly connected to plural wafers 有权
    具有直接连接到多个晶片的互连电极的封装芯片

    公开(公告)号：US07786573B2

    公开(公告)日：2010-08-31

    申请号：US11481012

    申请日：2006-07-06

    申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    IPC分类号： H01L23/34 ,  H01R12/16 ,  H05K1/11

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

    摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

    摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

    Method of fabricating one-way transparent optical system
    7.
    发明授权
    Method of fabricating one-way transparent optical system 有权
    制造单向透明光学系统的方法

    公开(公告)号：US07625693B2

    公开(公告)日：2009-12-01

    申请号：US11295636

    申请日：2005-12-07

    申请人： O-gweon Seo ,  Kae-dong Back ,  Chang-seung Lee ,  Kyu-sik Kim ,  Duck-su Kim ,  Byoung-ho Cheong

    发明人： O-gweon Seo ,  Kae-dong Back ,  Chang-seung Lee ,  Kyu-sik Kim ,  Duck-su Kim ,  Byoung-ho Cheong

    IPC分类号： G03F1/00

    CPC分类号： G02B5/003 ,  G02B1/11 ,  G02B3/0006 ,  G02B3/0018 ,  G03C1/00

    摘要： A method of fabricating a one-way transparent optical system by which external light is effectively intercepted and internal light passes nearly without loss is provided. The method includes: forming a silver halide on a transparent substrate; aligning a mask in which a predetermined pattern is formed, on the transparent substrate and exposing the silver halide using the mask; developing and fixing the exposed silver halide and forming a plurality of light-absorbing materials on the transparent substrate; and forming protrusion structures having a shape of a convex lens shape for refracting incident light toward a corresponding light-absorbing material of the light-absorbing materials, on the transparent substrate on which the light-absorbing materials are formed.

    摘要翻译： 提供了一种制造单向透明光学系统的方法，通过该方法可以有效地遮断外部光线，并且内部光线几乎没有损失。 该方法包括：在透明基板上形成卤化银; 将形成有预定图案的掩模对准在透明基板上，并使用掩模曝光卤化银; 显影和固定曝光的卤化银并在透明基板上形成多个光吸收材料; 以及在其上形成有光吸收材料的透明基板上形成具有用于将入射光折射到相应的光吸收材料的光吸收材料的凸透镜形状的突起结构。

    CHARGING DEVICE AND ELECTROPHOTOGRAPHIC IMAGE FORMING APPARATUS INCLUDING THE SAME
    8.
    发明申请
    CHARGING DEVICE AND ELECTROPHOTOGRAPHIC IMAGE FORMING APPARATUS INCLUDING THE SAME 审中-公开
    充电装置和电子图像形成装置，包括它们

    公开(公告)号：US20110058852A1

    公开(公告)日：2011-03-10

    申请号：US12876385

    申请日：2010-09-07

    申请人： Hee-moon Jeong ,  Kae-dong Back ,  Jin-ho Lee

    发明人： Hee-moon Jeong ,  Kae-dong Back ,  Jin-ho Lee

    IPC分类号： G03G15/02

    CPC分类号： G03G15/0208 ,  G03G15/0291 ,  G03G2215/02

    摘要： A charging device and an electrophotographic image forming apparatus including the same. A charging electrode of the charging device includes a porous insulating layer including a plurality of hollow rods vertically formed on a substrate formed of a conductive material, and a conductive nano structure formed in the hollow rods of the porous insulating layer. A grid electrode is supported by a spacer and is separated from the nano structure of the charging electrode. Furthermore, the charging electrode of the charging device may include a plurality of protrusions formed on a substrate, a porous insulating layer formed on the plurality of protrusions, and a conductive nano structure formed in hollow rods of the porous insulating layer.

    摘要翻译： 一种充电装置和包括该充电装置的电子照相成像装置。 充电装置的充电电极包括多孔绝缘层，多孔绝缘层包括垂直形成在由导电材料形成的基板上的多个中空棒，以及形成在多孔绝缘层的中空棒中的导电纳米结构。 栅极由间隔物支撑并与充电电极的纳米结构分离。 此外，充电装置的充电电极可以包括形成在基板上的多个突起，形成在多个突起上的多孔绝缘层，以及形成在多孔绝缘层的中空棒中的导电纳米结构。

    Image drum and a manufacturing method thereof
    9.
    发明申请
    Image drum and a manufacturing method thereof 审中-公开
    图像鼓及其制造方法

    公开(公告)号：US20070024691A1

    公开(公告)日：2007-02-01

    申请号：US11397703

    申请日：2006-04-05

    申请人： Kyu-ho Shin ,  Won-kyoung Choi ,  Jong-kwang Kim ,  Kae-dong Back ,  Chang-youl Moon

    发明人： Kyu-ho Shin ,  Won-kyoung Choi ,  Jong-kwang Kim ,  Kae-dong Back ,  Chang-youl Moon

    IPC分类号： B41J2/39

    CPC分类号： B41J2/395 ,  G03G15/348 ,  G03G2217/0075

    摘要： An image drum and method of producing the same is provided. The drum includes a drum body having a pair of semi-cylindrical members, each being oppositely bonded and having a bonding surface having electrodes being separated from one another by insulating areas, and line electrodes formed on the periphery; a control unit including conductive parts corresponding to the line electrodes, and nonconductive parts interposed between the conductive parts, and disposed inside the drum body; and a connecting member electrically coupling the line electrodes to the control unit. The method includes cutting a cylindrical member into two semi-cylindrical members; oxidizing the surfaces of the members; forming electrodes on each of the cut surfaces; partially oxidizing a substrate; bonding the two semi-cylindrical members across the substrate such that the electrodes and the conductive parts couple together; and forming line electrodes on the periphery of the members.

    摘要翻译： 提供了一种图像鼓及其制造方法。 滚筒包括具有一对半圆柱形构件的鼓体，每个半圆柱体构件相对地接合并且具有通过绝缘区域彼此分离的电极和在周边上形成的线电极的接合表面; 控制单元，其包括对应于所述线电极的导电部分，以及插入在所述导电部件之间的非导电部件，并且设置在所述鼓体内; 以及将线路电极电耦合到控制单元的连接构件。 该方法包括将圆柱形构件切割成两个半圆柱形构件; 氧化构件的表面; 在每个切割表面上形成电极; 部分氧化底物; 将两个半圆柱形构件跨过衬底结合，使得电极和导电部件耦合在一起; 以及在所述构件的周边上形成线电极。