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41 条记录 (耗时 0.041 秒)

    Wafer level packaging cap and fabrication method thereof
    1.
    发明授权
    Wafer level packaging cap and fabrication method thereof 有权
    晶圆级封装盖及其制造方法

    公开(公告)号：US07579685B2

    公开(公告)日：2009-08-25

    申请号：US11339500

    申请日：2006-01-26

    申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    IPC分类号： H01L23/12 ,  H01L23/043

    CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

    摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

    Packaging chip and packaging method thereof
    5.
    发明申请
    Packaging chip and packaging method thereof 失效
    包装芯片及其包装方法

    公开(公告)号：US20060273444A1

    公开(公告)日：2006-12-07

    申请号：US11390220

    申请日：2006-03-28

    申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    IPC分类号： H01L23/48

    CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

    摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

    摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

    Packaging chip and packaging method thereof
    7.
    发明授权
    Packaging chip and packaging method thereof 失效
    包装芯片及其包装方法

    公开(公告)号：US07408257B2

    公开(公告)日：2008-08-05

    申请号：US11390220

    申请日：2006-03-28

    申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    IPC分类号： H01L23/04

    CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

    摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

    摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

    Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor
    9.
    发明申请
    Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor 有权
    具有直接连接到多个晶片的互连电极的封装芯片及其制造方法

    公开(公告)号：US20070013058A1

    公开(公告)日：2007-01-18

    申请号：US11481012

    申请日：2006-07-06

    申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    IPC分类号： H01L23/34

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

    摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

    摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

    Packaging chip having interconnection electrodes directly connected to plural wafers
    10.
    发明授权
    Packaging chip having interconnection electrodes directly connected to plural wafers 有权
    具有直接连接到多个晶片的互连电极的封装芯片

    公开(公告)号：US07786573B2

    公开(公告)日：2010-08-31

    申请号：US11481012

    申请日：2006-07-06

    申请人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    发明人： Min-seog Choi ,  Kae-dong Back ,  In-sang Song ,  Woon-bae Kim ,  Byung-gil Jeong ,  Kyu-dong Jung

    IPC分类号： H01L23/34 ,  H01R12/16 ,  H05K1/11

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H9/0547

    摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

    摘要翻译： 形成有多个晶片的封装芯片。 封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。 多个晶片中的至少一个或多个在其上安装预定的电路装置。 此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。 同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。 因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。