公开(公告)号：US20050122246A1

公开(公告)日：2005-06-09

申请号：US11042006

申请日：2005-01-25

申请人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

发明人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC分类号： G11C7/06 ,  G11C7/14 ,  H03M1/12

CPC分类号： G11C7/065 ,  G11C7/14

摘要： A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

公开(公告)号：US06747695B1

公开(公告)日：2004-06-08

申请号：US08985838

申请日：1997-12-05

申请人： Morteza Afghahi

发明人： Morteza Afghahi

IPC分类号： H04N5217

CPC分类号： H04N5/361

摘要： An integrated CMOS image sensor comprising pixel rows integrated on a substrate, each pixel row having pixel circuits, each pixel circuit providing a voltage signal in response to absorbed photons; and an opaque layer deposited above the pixel rows to define a set of dark pixels for each pixel row. For each pixel row, dark voltage signals indicative of the voltage signals provided by the set of dark pixels are stored and used to dark correct the voltage signals from the other pixels. The image sensor also comprises voltage-to-current converters for converting the voltage signals to currents for all pixel columns for each frame and followers to reduce the voltage swings on the outputs of the voltage-to-current converters. The currents are multiplexed in serial fashion to a current-to-voltage converter. The output of the current-to-voltage converter provides the dark voltage signals.

摘要翻译： 一种集成CMOS图像传感器，包括集成在衬底上的像素行，每个像素行具有像素电路，每个像素电路响应于吸收的光子提供电压信号; 以及沉积在像素行上方的不透明层，以限定每个像素行的一组暗像素。 对于每个像素行，存储指示由该组暗像素提供的电压信号的暗电压信号，并用于暗校正来自其它像素的电压信号。 图像传感器还包括电压 - 电流转换器，用于将电压信号转换成针对每个帧的所有像素列的电流和跟随器，以减小电压 - 电流转换器的输出端上的电压摆幅。 电流以串联方式复用到电流 - 电压转换器。 电流 - 电压转换器的输出提供暗电压信号。

公开(公告)号：US20070165435A1

公开(公告)日：2007-07-19

申请号：US11431439

申请日：2006-05-10

申请人： Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

发明人： Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

摘要翻译： 在一个实施例中，提供了一种CAM，其包括： 分组存储单词的多个存储单元，其中所述存储单元组织成多个纹波组，每个纹波组包括复合逻辑门，其配置用于确定所述纹波组的存储单元的存储内容是否与 一个比较字，如果纹波组的使能输入被断言，则每个复合逻辑门在该确定指示匹配时将输出置为有效，波纹组从第一纹波组布置到最后纹波组，使得来自第一 纹波组的复杂逻辑门用作第二纹波组的复杂逻辑门等的使能输入，使得来自下一个到最后纹波组的复杂逻辑门的输出用作最后纹波组的复杂逻辑门的使能输入 。

公开(公告)号：US20050146979A1

公开(公告)日：2005-07-07

申请号：US11058154

申请日：2005-02-15

申请人： Esin Terzioglu ,  Morteza Afghahi

发明人： Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C7/06 ,  G11C8/00

CPC分类号： G11C7/06

摘要： A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

摘要翻译： 提供异步复位，冗余或两者的解码器。 具有冗余的异步复位解码器。 解码器具有响应于时钟信号的同步部分; 与异步电路耦合的异步部分; 反馈复位部分，其响应于异步复位信号，基本上将同步部分与异步部分耦合并插入在同步部分之间; 信号输入; 与第一存储器单元组耦合的第一存储器输出; 与第二存储单元组耦合的第二存储器输出; 以及耦合在信号输入，第一存储器输出和第二存储器输出之间的选择器。 该解码器可以是面向行的存储器，并且因此提供具有行冗余的异步可重置行解码器，或者具有列冗余的异步可重置列解码器。

公开(公告)号：US6144195A

公开(公告)日：2000-11-07

申请号：US378626

申请日：1999-08-20

申请人： Morteza Afghahi ,  Yueming He

发明人： Morteza Afghahi ,  Yueming He

IPC分类号： G05F1/46 ,  G05F3/16

CPC分类号： G05F1/467

摘要： An embodiment of the invention is directed to a voltage regulator that provides a conditioned reference voltage with high supply noise rejection. A reference circuit provides an input reference voltage. An operational amplifier (opamp) has a first opamp input coupled to the reference circuit, a second opamp input, and an opamp output to provide the conditioned reference voltage based on the input reference voltage. A differential MOS amplifier has a first input coupled to the opamp output and an output coupled to the second opamp input. The reference voltage is conditioned in accordance with the size of transistors in the differential amplifier. The voltage regulator may be used in different types of analog-to-digital converters, including those built for use with camera chips.

摘要翻译： 本发明的实施例涉及一种提供具有高电源噪声抑制的调节参考电压的电压调节器。 参考电路提供输入参考电压。 运算放大器（运算放大器）具有耦合到参考电路的第一运算放大器输入端，第二运算放大器输入端和运算放大器输出端，用于基于输入参考电压提供经调节的参考电压。 差分MOS放大器具有耦合到运算放大器输出的第一输入和耦合到第二运算放大器输入的输出。 参考电压根据差分放大器中晶体管的尺寸进行调节。 电压调节器可以用于不同类型的模拟 - 数字转换器，包括用于与相机芯片一起使用的转换器。

公开(公告)号：US6124754A

公开(公告)日：2000-09-26

申请号：US303486

申请日：1999-04-30

申请人： Morteza Afghahi

发明人： Morteza Afghahi

IPC分类号： G05F3/24 ,  G05F3/26 ,  G05F1/10

CPC分类号： G05F3/245 ,  G05F3/262

摘要： A reference circuit includes a first resistive element and a current source. The first resistive element is adapted to produce an output voltage based on a first current and a resistance of the first resistive element. The resistance of the first resistive element is a function of a temperature of the current. The current source includes a second resistive element that has a resistance that is a function of the temperature. The current source is adapted to adjust the first current to minimize variation of the output voltage with the temperature based on the resistance of the second resistive element.

摘要翻译： 参考电路包括第一电阻元件和电流源。 第一电阻元件适于基于第一电阻元件的第一电流和电阻产生输出电压。 第一电阻元件的电阻是电流的温度的函数。 电流源包括具有作为温度的函数的电阻的第二电阻元件。 电流源适于调整第一电流以最小化基于第二电阻元件的电阻的温度的输出电压的变化。

公开(公告)号：US20050128831A1

公开(公告)日：2005-06-16

申请号：US11040976

申请日：2005-01-21

申请人： Morteza Afghahi ,  Bibhudatta Sahoo

发明人： Morteza Afghahi ,  Bibhudatta Sahoo

IPC分类号： G11C15/04 ,  G11C7/00

CPC分类号： G11C15/04

摘要： A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14 and 16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.

摘要翻译： 内容可寻址存储单元（10）包括从预定的电源电压（VDD）操作的电路（20），用于在第一点（35）存储第一位数据，在第二点（36）存储第二位互补数据 ）。 响应于第一和第二位之间的预定关系以及在第一和第二行（14和16）上传输的第三和第四测试位，包括第一门（42）的第一晶体管（40）可切换到第一和第二状态。 第二和第三晶体管（50,60）包括耦合到第一线路（14）和第二线路（16）的门（52,62），并且包括将第一和第二点耦合到的线路路径（54,56,64,66） 第一个门

公开(公告)号：US20050018510A1

公开(公告)日：2005-01-27

申请号：US10925495

申请日：2004-08-24

申请人： Esin Terzioglu ,  Morteza Afghahi

发明人： Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06

摘要： A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor. Furthermore, the charge-sharing circuit includes a precharging circuit, and a charge reservoir, which selectively sources and sinks charge when the sense amplifier is used. The sense amplifier is a latch-type differential sense amplifier.

摘要翻译： 适于感测全局位线上的输入信号的读出放大器，具有放大器偏移消除网络和偏移均衡网络。 放大器偏移消除网络减轻固有偏移信号值，动态偏移信号值或二者，但是产生残余偏移信号值，其基本上被偏移均衡网络消除。 当读出放大器未使用时，读出放大器还可以包括隔离电路，以将读出放大器与对应的全局位线隔离。 此外，当感测放大器被激活时，电荷共享电路用于在位线之间共享电荷，从而在位线上产生有限的电压摆幅。 读出放大器使用具有多个预充电和平衡晶体管的放大器偏移消除网络，以及具有至少一个平衡晶体管的偏移均衡网络。 此外，电荷共享电路包括预充电电路和电荷储存器，当使用读出放大器时，电荷储存器选择性地源和吸收电荷。 读出放大器是锁存型差分读出放大器。

公开(公告)号：US06232757B1

公开(公告)日：2001-05-15

申请号：US09635296

申请日：2000-08-10

申请人： Morteza Afghahi ,  Yueming He

发明人： Morteza Afghahi ,  Yueming He

IPC分类号： G05F316

CPC分类号： G05F1/467

摘要： An embodiment of the invention is directed to a voltage regulator that provides a conditioned reference voltage with high supply noise rejection. A reference circuit provides an input reference voltage. An operational amplifier (opamp) has a first opamp input coupled to the reference circuit, a second opamp input, and an opamp output to provide the conditioned reference voltage based on the input reference voltage. A differential MOS amplifier has a first input coupled to the opamp output and an output coupled to the second opamp input. The reference voltage is conditioned in accordance with the size of transistors in the differential amplifier. The voltage regulator may be used in different types of analog-to-digital converters, including those built for use with camera chips.

摘要翻译： 本发明的实施例涉及一种提供具有高电源噪声抑制的调节参考电压的电压调节器。 参考电路提供输入参考电压。 运算放大器（运算放大器）具有耦合到参考电路的第一运算放大器输入端，第二运算放大器输入端和运算放大器输出端，用于基于输入参考电压提供经调节的参考电压。 差分MOS放大器具有耦合到运算放大器输出的第一输入和耦合到第二运算放大器输入的输出。 参考电压根据差分放大器中晶体管的尺寸进行调节。 电压调节器可以用于不同类型的模拟 - 数字转换器，包括用于与相机芯片一起使用的转换器。

公开(公告)号：US06204795B1

公开(公告)日：2001-03-20

申请号：US09227994

申请日：1999-01-08

申请人： Morteza Afghahi

发明人： Morteza Afghahi

IPC分类号： H03M150

CPC分类号： H03M1/48 ,  H04N5/376

摘要： A method is provided having the steps of receiving a first pixel signal; generating a first set of bits representative of the first pixel signal; receiving a second pixel signal; and, generating a second set of bits representative of a difference between the first pixel signal and the second pixel signal. An apparatus and system for performing the above method is also provided.

摘要翻译： 提供一种具有接收第一像素信号的步骤的方法; 产生表示第一像素信号的第一组位; 接收第二像素信号; 以及产生代表第一像素信号和第二像素信号之间的差的第二组位。 还提供了用于执行上述方法的装置和系统。