公开(公告)号：US5896317A

公开(公告)日：1999-04-20

申请号：US852353

申请日：1997-05-07

申请人： Motoharu Ishii ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

发明人： Motoharu Ishii ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/10

摘要： It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.

摘要翻译： 假定，每个存储器单元阵列中，第一位线对应于所选地址。 在这种情况下，仅第一位线上的电位达到H电平。 要加载的数据被提供给通过数据线对应于所述第一位线的锁存电路独立于位线的布置。 每次完成1字节数据的加载后，所有位线都将被复位。 因此，即使当数据要被从所述数据被装载之后立即进入锁存电路，或可以防止已经载入到锁存电路中的数据破坏的存储器单元阵列读取来执行快速的数据读取。 此外，可以减少电路面积。

公开(公告)号：US5521864A

公开(公告)日：1996-05-28

申请号：US385866

申请日：1995-02-09

申请人： Shinichi Kobayashi ,  Hiroaki Nakai ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

发明人： Shinichi Kobayashi ,  Hiroaki Nakai ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/34 ,  G11C29/50 ,  G11C11/34

CPC分类号： G11C16/3459 ,  G11C16/3454 ,  G11C29/50 ,  G11C29/50004 ,  G06F2201/81 ,  G11C16/04

摘要： A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.

摘要翻译： 位线复位晶体管复位要被写入验证的多个位线的每一个第二位线。 此时，传输门将列锁存器与未分配位线断开。 然后，根据列锁存器的数据对未复位位线进行预充电，同时向字线施加验证电压。 然后，源极线晶体管接地源极线，并且位线连接到列锁存器，使得与存储器单元的阈值电压值对应的数据由列锁存器保持，写入验证操作是 执行。

公开(公告)号：US6069518A

公开(公告)日：2000-05-30

申请号：US352143

申请日：1994-12-01

申请人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

发明人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073 ,  G11C16/30

摘要： In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

摘要翻译： 响应于从驱动器提供的互补时钟信号，电荷泵操作以提供作为下变频负电压的输出电压。 该输出电压和预定的正参考电压之间的电压由电容器分压。 将电容分压正电压施加到比较器，由此将参考电压与上述正电压进行比较。 比较器的输出信号被施加到驱动器。 作为响应，驱动器控制电荷泵的操作，由此输出电压被钳位在预定的电压电平以便输出。

公开(公告)号：US20100014355A1

公开(公告)日：2010-01-21

申请号：US12571917

申请日：2009-10-01

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C16/04

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

摘要翻译： 在非易失性存储单元中，选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构，并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合，将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小，从而可以减少电流消耗，并且可以减小电压发生器的布局面积。 因此，提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。

公开(公告)号：US07791943B2

公开(公告)日：2010-09-07

申请号：US12571917

申请日：2009-10-01

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

摘要翻译： 在非易失性存储单元中，选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构，并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合，将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小，从而可以减少电流消耗，并且可以减小电压发生器的布局面积。 因此，提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。

公开(公告)号：US20080144383A1

公开(公告)日：2008-06-19

申请号：US12010020

申请日：2008-01-18

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C16/06

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

公开(公告)号：US20080099825A1

公开(公告)日：2008-05-01

申请号：US11976496

申请日：2007-10-25

申请人： Motoharu Ishii ,  Kiyohiko Sakakibara

发明人： Motoharu Ishii ,  Kiyohiko Sakakibara

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a principal surface, memory transistors, and selection transistors. Each of the memory transistors has a floating gate and a control gate that are formed by lamination with each other on the principal surface. Each of the selection transistors has a lower gate layer and an upper gate layer that are formed by lamination with each other on the principal surface, and is contained in a memory cell together with one of the memory transistors. The lower gate layer is separated for each one of the selection transistors. The upper gate layer is owned commonly by the selection transistors and is electrically connected to the lower gate layer of each of the selection transistors. Therefore, it is possible to prevent short-circuiting of the selection transistors and the memory transistors.

摘要翻译： 非易失性半导体存储器件包括具有主表面的半导体衬底，存储晶体管和选择晶体管。 每个存储晶体管具有通过在主表面上彼此层压而形成的浮动栅极和控制栅极。 每个选择晶体管具有通过在主表面上彼此层叠而形成的下栅极层和上栅极层，并且与存储晶体管中的一个一起被包含在存储单元中。 对于每个选择晶体管分离下栅极层。 上栅极层由选择晶体管共同拥有，并且电连接到每个选择晶体管的下栅极层。 因此，可以防止选择晶体管和存储晶体管的短路。

公开(公告)号：US20060245254A1

公开(公告)日：2006-11-02

申请号：US11411933

申请日：2006-04-27

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

摘要翻译： 在非易失性存储单元中，选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构，并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合，将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小，从而可以减少电流消耗，并且可以减小电压发生器的布局面积。 因此，提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。

公开(公告)号：US20050012138A1

公开(公告)日：2005-01-20

申请号：US10757438

申请日：2004-01-15

申请人： Seiichi Endo ,  Motoharu Ishii

发明人： Seiichi Endo ,  Motoharu Ishii

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate having a main surface; a pair of p-type impurity diffused regions, formed at the main surface of the semiconductor substrate to serve as source/drain; a floating gate formed on a region of the semiconductor substrate lying between the paired p-type impurity diffused regions, with a tunnel insulating layer interposed between the floating gate and the region of the semiconductor substrate; and an impurity diffused control region formed at the main surface of the semiconductor substrate to control a potential of the floating gate. Accordingly, a nonvolatile semiconductor device can be obtained in which data can be electrically erased and written at a low voltage.

摘要翻译： 非易失性半导体存储器件包括：具有主表面的半导体衬底; 一对p型杂质扩散区，形成在半导体衬底的主表面上，用作源极/漏极; 形成在位于所述一对p型杂质扩散区域之间的所述半导体衬底的区域上的浮置栅极和介于所述浮置栅极和所述半导体衬底的区域之间的隧道绝缘层; 以及形成在半导体衬底的主表面处的杂质扩散控制区域，以控制浮置栅极的电位。 因此，可以获得能够以低电压电擦除和写入数据的非易失性半导体器件。

公开(公告)号：US07342828B2

公开(公告)日：2008-03-11

申请号：US11411933

申请日：2006-04-27

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

摘要翻译： 在非易失性存储单元中，选择晶体管与存储单元晶体管串联连接。 选择晶体管形成双层栅极结构，并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合，将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小，从而可以减少电流消耗，并且可以减小电压发生器的布局面积。 因此，提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。