公开(公告)号：US06859066B1

公开(公告)日：2005-02-22

申请号：US10377320

申请日：2003-02-28

申请人： Arifur Rahman ,  William Andrews ,  Mou C. Lin

发明人： Arifur Rahman ,  William Andrews ,  Mou C. Lin

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/017581 ,  H03K19/1778 ,  H03K19/17788

摘要： A bank of input/output buffers are configured such that each input buffer in the bank may select from a plurality of voltage references during single-ended operation. Similarly, the pad associated with each input buffer may serve to supply one of the voltage references for other input buffers within the bank.

摘要翻译： 一组输入/输出缓冲器被配置为使得单行中的每个输入缓冲器可以在单端操作期间从多个电压基准中选择。 类似地，与每个输入缓冲器相关联的焊盘可以用于为bank内的其它输入缓冲器提供一个电压基准。

公开(公告)号：US06967500B1

公开(公告)日：2005-11-22

申请号：US10397669

申请日：2003-03-26

申请人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

发明人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

IPC分类号： H03K17/16 ,  H04L25/02

CPC分类号： H04L25/0278 ,  H03K17/164

摘要： An electronic circuit with programmable terminations includes a circuit block, signal pads coupled to the circuit block, programmable termination circuits each associated with a corresponding one of the signal pads, and a reference circuit operative to generate one or more control signals for application to the programmable termination circuits. A given one of the programmable termination circuits is configurable independently of at least one of the other programmable termination circuits into one of a plurality of termination states. Preferably, the programmable termination circuits are each independently configurable to provide a particular termination resistance and a particular supply terminal connection type for the associated signal pad. The invention is particularly well suited for use in integrated circuit applications, such as, for example, those involving FPGAs, FPSCs and ASICs.

摘要翻译： 具有可编程端接的电子电路包括电路块，耦合到电路块的信号焊盘，每个与相应的一个信号焊盘相关联的可编程终端电路，以及可用于产生一个或多个控制信号以用于可编程 终端电路。 可编程终端电路中的给定一个可独立于至少一个其他可编程终端电路配置成多个终止状态之一。 优选地，可编程终端电路各自独立地可配置以提供特定的终端电阻和用于相关联的信号焊盘的特定供电端子连接类型。 本发明特别适用于集成电路应用，例如涉及FPGA，FPSC和ASIC的那些应用。

公开(公告)号：US06943583B1

公开(公告)日：2005-09-13

申请号：US10671378

申请日：2003-09-25

申请人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

发明人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。

公开(公告)号：US07605609B1

公开(公告)日：2009-10-20

申请号：US11957598

申请日：2007-12-17

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K19/0175

CPC分类号： H03K3/356165

摘要： In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

摘要翻译： 在本发明的一个实施例中，可编程电平转换器可被选择性地配置为以高速模式或低功率模式工作。 在两种模式中，电平移位器将一个电源域中的输入信号转换为另一个电源域中的输出信号。 在高速模式中，p型器件被配置为电流镜放大器，为电平转换器提供相对较快的开关速度。 在低功耗模式中，相同的p型器件被配置为交叉耦合的锁存器，其为电平移位器提供相对较低的功耗。 选择性使能的n型器件提供具有较大有效n型器件的低功耗模式，以在低功耗模式下翻转由p型器件形成的交叉耦合锁存器。

公开(公告)号：US07586325B1

公开(公告)日：2009-09-08

申请号：US11949130

申请日：2007-12-03

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00369 ,  H03K17/14 ,  H03K19/17748 ,  H03K19/1778

摘要： In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage. In one implementation, the application circuitry is an output driver having source and sink driver blocks, where driver-control circuitry controls the configuration of the source driver block based on the selected output-driver power supply voltage, a source PT-control signal, and a selected drive strength, while controlling the configuration of the sink driver block based on the selected output-driver power supply voltage, a sink PT-control signal, and a selected drive strength.

摘要翻译： 在一个实施例中，集成电路具有可操作的多个可用电源电压中的任何一个的可配置应用电路。 以PT参考电压工作的PT控制电路产生指示过程和温度变化的PT控制信号。 应用控制电路基于用于应用电路和PT控制信号的所选择的电源电压控制应用电路的配置，其中所选择的电源电压独立于PT参考电压。 在一个实现中，应用电路是具有源和接收器驱动器块的输出驱动器，其中驱动器控制电路基于所选择的输出驱动器电源电压来控制源极驱动器模块的配置，源PT控制信号和 选择的驱动强度，同时基于所选择的输出驱动器电源电压，信宿PT控制信号和选择的驱动强度来控制接收器驱动器块的配置。

公开(公告)号：US07495467B2

公开(公告)日：2009-02-24

申请号：US11300886

申请日：2005-12-15

申请人： Mou C. Lin ,  William B. Andrews ,  John A. Schadt

发明人： Mou C. Lin ,  William B. Andrews ,  John A. Schadt

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H01L28/20

摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

摘要翻译： 在本发明的一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及被设计成控制每个端接方案用于处理电压的校准电路 ，和温度（PVT）变化。 校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。 每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。 感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

公开(公告)号：US07161862B1

公开(公告)日：2007-01-09

申请号：US10996283

申请日：2004-11-22

申请人： Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

发明人： Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

IPC分类号： G11C7/02

CPC分类号： G11C7/065

摘要： A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.

摘要翻译： 存储读出放大器包括输出和补码输出。 读出放大器被配置为使得驱动位线低的存储单元通过使补码输出上拉而使位线锁存为低电平，并且驱动补码位线的存储单元为低电平使得能够将补码位线锁存 通过启用输出的上拉。

公开(公告)号：US07714608B1

公开(公告)日：2010-05-11

申请号：US12370039

申请日：2009-02-12

申请人： Mou C. Lin ,  William B. Andrews ,  John A. Schadt

发明人： Mou C. Lin ,  William B. Andrews ,  John A. Schadt

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H01L28/20

摘要： In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

摘要翻译： 在一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及设计成控制处理，电压和温度的每个端接方案的校准电路 （PVT）变化。 校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。 每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。 感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

公开(公告)号：US07443192B1

公开(公告)日：2008-10-28

申请号：US11643288

申请日：2006-12-21

申请人： William B. Andrews ,  Mou C. Lin ,  John A. Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John A. Schadt

IPC分类号： H03K19/003

CPC分类号： H03K19/00369

摘要： An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

摘要翻译： 一种改进的输出缓冲器，具有数字输出摆幅控制和补偿制造工艺变化。 输出回转是通过将数字驱动信号排列成并联的输出晶体管来实现的。 在一个实施例中，预驱动器通过使用串行数字逻辑门的传播延迟来排序驱动信号，以减少电源下降和/或地面反弹。 输出晶体管基本上同时截止，以避免在输出缓冲器改变状态时不期望的电源DC电流流动。 可编程地配置可以在任何给定时间导通的并联晶体管的数量允许用户补偿制造工艺变化并确定缓冲器的输出阻抗/驱动能力。

公开(公告)号：US07230810B1

公开(公告)日：2007-06-12

申请号：US11007954

申请日：2004-12-09

申请人： William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

发明人： William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

IPC分类号： H02H9/04

CPC分类号： H01L27/0285

摘要： An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.

摘要翻译： 具有晶体管器件和过电压保护电路的集成电路。 晶体管器件以具有指定工作电压范围的技术实现，该晶体管器件具有栅极，漏极，源极和源极节点以及具有指定最大电压的规定工作电压范围。 过电压保护电路分别适用于门和电池的电压。 如果施加到至少一个漏极和源极节点的至少一个沟道电压超过规定的最大电压，则过电压保护电路控制栅极电压和电池电压中的至少一个以抑制一个或多个不利影响 晶体管器件。