Methods of screening foods for nutraceuticals
    2.
    发明授权
    Methods of screening foods for nutraceuticals 失效
    筛选营养品食品的方法

    公开(公告)号:US5955269A

    公开(公告)日:1999-09-21

    申请号:US670826

    申请日:1996-06-20

    摘要: The invention relates to an assay system for screening nutraceuticals, i.e., foods or food substances that occur naturally, or that are produced during processing which are capable of modulating in a subject the expression of one or more genes associated with a disease or undesirable physical condition. The nutraceuticals identified by the screening assays can be incorporated into compositions which may be administered to a subject to treat or prevent a disease or undesirable condition, or otherwise to improve the health of the subject. The invention further provides methods for modifying the amount of nutraceuticals in raw and processed foods or food substances.

    摘要翻译: 本发明涉及用于筛选营养品的测定系统,即天然存在的或在加工过程中产生的食物或食物,其能够在受试者中调节与疾病或不期望的身体状况相关的一种或多种基因的表达 。 通过筛选测定鉴定的营养药物可以并入可以施用于受试者以治疗或预防疾病或不良状况或以其他方式改善受试者健康的组合物中。 本发明进一步提供了用于改变生加工食品或食品中营养药物量的方法。

    Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
    3.
    发明申请
    Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
    将算法元素下载到协处理器的系统和方法以及相应的技术

    公开(公告)号:US20050122332A1

    公开(公告)日:2005-06-09

    申请号:US10987144

    申请日:2004-11-12

    摘要: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

    摘要翻译: 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线,本发明提供了一类协处理设备,诸如图形处理器单元(GPU),为抽象或虚拟机提供改进的能力,用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制,使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列,为纹理和纹理贴图提供本地支持,并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频,可选地支持流模值,在像素着色器上提供寄存器存储元素,并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器,具有更多的片上寄存器存储,并且能够接收比任何现有顶点或像素着色器更大的程序,并在顶点和像素着色器中提供32位浮点数支持。

    Methods and system for general skinning via hardware accelerators

    公开(公告)号:US20050099417A1

    公开(公告)日:2005-05-12

    申请号:US10994867

    申请日:2004-11-22

    IPC分类号: G06T15/70 G06T15/00

    CPC分类号: G06T13/40

    摘要: Complex computer graphics forms and motions can be constructed either by hand or with motion or geometry capture technologies, once they are created, they are difficult to modify, particularly at runtime. Interpolation provides a way to leverage artist-generated source material. Methodologies for efficient runtime interpolation between multiple forms or multiple motion segments enables computers to perform more realistic animation in real-time. Shape interpolation is applied to predefined figures to create smoothly skinned figures that deform in natural ways. Predefined figures are selected using a search technique that reduces the amount of interpolation required to produce real-time animation.

    Methods and system for general skinning via hardware accelerators
    6.
    发明申请
    Methods and system for general skinning via hardware accelerators 失效
    通过硬件加速器进行一般剥皮的方法和系统

    公开(公告)号:US20050140680A1

    公开(公告)日:2005-06-30

    申请号:US10980934

    申请日:2004-11-04

    IPC分类号: G06T15/70

    CPC分类号: G06T13/40

    摘要: Complex computer graphics forms and motions can be constructed either by hand or with motion or geometry capture technologies, once they are created, they are difficult to modify, particularly at runtime. Interpolation provides a way to leverage artist-generated source material. Methodologies for efficient runtime interpolation between multiple forms or multiple motion segments enables computers to perform more realistic animation in real-time. Shape interpolation is applied to predefined figures to create smoothly skinned figures that deform in natural ways. Predefined figures are selected using a search technique that reduces the amount of interpolation required to produce real-time animation.

    摘要翻译: 复杂的计算机图形形式和运动可以手动或运动或几何捕获技术构建,一旦创建,它们很难修改,特别是在运行时。 插值提供了一种利用艺术家生成的素材的方法。 用于多个表单或多个运动段之间高效运行时插值的方法使计算机能够实时执行更逼真的动画。 形状插值应用于预定义的图形,以创建平滑的皮肤图形,以自然的方式变形。 使用减少产生实时动画所需的插值量的搜索技术来选择预定义的数字。

    API communications for vertex and pixel shaders

    公开(公告)号:US20050140669A1

    公开(公告)日:2005-06-30

    申请号:US10981963

    申请日:2004-11-05

    IPC分类号: G06T15/00 G06T15/80 G06T1/00

    摘要: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

    Method and system for defining and controlling algorithmic elements in a graphics display system

    公开(公告)号:US20050086317A1

    公开(公告)日:2005-04-21

    申请号:US10971450

    申请日:2004-10-22

    CPC分类号: G06T15/005

    摘要: An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

    API communications for vertex and pixel shaders

    公开(公告)号:US20050030312A1

    公开(公告)日:2005-02-10

    申请号:US10937031

    申请日:2004-09-09

    摘要: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

    MATRIX-BASED SCANS ON PARALLEL PROCESSORS
    10.
    发明申请
    MATRIX-BASED SCANS ON PARALLEL PROCESSORS 审中-公开
    基于MATRIX的扫描并行处理器

    公开(公告)号:US20100076941A1

    公开(公告)日:2010-03-25

    申请号:US12206758

    申请日:2008-09-09

    IPC分类号: G06F17/30

    CPC分类号: G06F17/10

    摘要: A system and method for performing a scan of an input sequence in a parallel processor having a shared register file. A two dimensional matrix is generated, having a number of rows representing a number of threads and a number of columns based on the input sequence block size and the number of rows. One or more padding columns may be added to the matrix to avoid or reduce memory bank conflicts. A first traversal of the rows performs a reduction or a scan of each of the rows in parallel, storing the reduction values. The reduction values are used during a second traversal to propagate the reduction values. In a segmented scan, propagation is selectively performed based on flags representing segment boundaries.

    摘要翻译: 一种用于在具有共享寄存器文件的并行处理器中执行对输入序列的扫描的系统和方法。 生成二维矩阵,其具有表示线程数量的多行和基于输入序列块大小和行数的列数。 可以将一个或多个填充列添加到矩阵中以避免或减少存储体冲突。 行的第一次遍历对并行的每行进行缩小或扫描,存储缩小值。 在第二次遍历期间使用缩小值来传播缩小值。 在分段扫描中,基于表示段边界的标志选择性地执行传播。