摘要:
An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.
摘要:
A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.
摘要:
The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold activity level. A least important cache line is located in the cache responsive to a determination that the threshold activity level is exceeded, wherein the least important cache line is located using a cache replacement scheme. It is determined whether the least important cache line is clean responsive to the determination that the threshold activity level is exceeded. The least important cache line is selected for replacement in the cache responsive to a determination that the least important cache line is clean. A clean cache line is located within a subset of the number of cache lines and selecting the clean cache line for replacement responsive to an absence of a determination that the least important cache line is not clean, wherein the each cache line in the subset is examined in ascending order of importance according to the cache replacement scheme.
摘要:
Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period.
摘要:
Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.
摘要:
The illustrative embodiments provide a method, a computer program product, and an apparatus for managing a cache. A probability of a future request for data to be stored in a portion of the cache by a thread is identified for each of the number of threads to form a number of probabilities. The data is stored with a rank in a number of ranks in the portion of the cache responsive to receiving the future request from the thread in the number of threads for the data. The rank is selected using the probability in the number of probabilities for the thread.
摘要:
A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.
摘要:
In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.
摘要:
Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period.
摘要:
The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold activity level. A least important cache line is located in the cache responsive to a determination that the threshold activity level is exceeded, wherein the least important cache line is located using a cache replacement scheme. It is determined whether the least important cache line is clean responsive to the determination that the threshold activity level is exceeded. The least important cache line is selected for replacement in the cache responsive to a determination that the least important cache line is clean. A clean cache line is located within a subset of the number of cache lines and selecting the clean cache line for replacement responsive to an absence of a determination that the least important cache line is not clean, wherein the each cache line in the subset is examined in ascending order of importance according to the cache replacement scheme.