公开(公告)号：US07200068B2

公开(公告)日：2007-04-03

申请号：US10330652

申请日：2002-12-27

申请人： Muhammad M. Khellah ,  Yibin Ye ,  Stephen H. Tang ,  Vivek De

发明人： Muhammad M. Khellah ,  Yibin Ye ,  Stephen H. Tang ,  Vivek De

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G06F9/30141 ,  G11C7/18

摘要： A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.

摘要翻译： 多端口寄存器包括通过输出晶体管将栅极耦合到数据输出线的全局位线（GBL）。 本地位线（LBL）将门耦合到第一寄存器堆单元和第二寄存器堆单元，所述第二寄存器堆单元布置成比第一寄存器堆单元靠近数据输出线。 第一寄存器堆单元中的至少一个晶体管具有比第二寄存器堆单元中的至少一个晶体管更强的驱动电流。 第一组的输出晶体管，栅极和第一寄存器堆单元中的至少一个具有比对应的输出晶体管更强的驱动电流，第二存储体的栅极和第一存储体的第一寄存器堆单元表示第二存储体更接近 到数据输出线。

公开(公告)号：US07280425B2

公开(公告)日：2007-10-09

申请号：US11239903

申请日：2005-09-30

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

摘要翻译： 一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物 存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

公开(公告)号：US07102951B2

公开(公告)日：2006-09-05

申请号：US10979605

申请日：2004-11-01

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

IPC分类号： G11C17/18

CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

摘要翻译： 包括一次性可编程反熔丝电池的不同实施例。 在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。 反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。 感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。 高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

公开(公告)号：US07355246B2

公开(公告)日：2008-04-08

申请号：US11268430

申请日：2005-11-07

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L29/76

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US07321502B2

公开(公告)日：2008-01-22

申请号：US10956285

申请日：2004-09-30

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

摘要翻译： 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

公开(公告)号：US06992339B2

公开(公告)日：2006-01-31

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L27/10

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US06906973B1

公开(公告)日：2005-06-14

申请号：US10746148

申请日：2003-12-24

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12

摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US07423899B2

公开(公告)日：2008-09-09

申请号：US10812894

申请日：2004-03-31

申请人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

发明人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C11/412

摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

摘要翻译： 提供具有多个存储单元的SRAM器件。 每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。 功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

公开(公告)号：US07342845B2

公开(公告)日：2008-03-11

申请号：US11320789

申请日：2005-12-30

申请人： Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz ,  Stephen H. Tang

发明人： Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz ,  Stephen H. Tang

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C5/147 ,  G11C11/413

摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

摘要翻译： 提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。 该装置可以包括存储器阵列，睡眠装置和钳位电路。 钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。

公开(公告)号：US07206249B2

公开(公告)日：2007-04-17

申请号：US10956195

申请日：2004-09-30

申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen H. Tang ,  Vivek K. De

发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen H. Tang ,  Vivek K. De

IPC分类号： G11C5/14

CPC分类号： G11C11/413

摘要： A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.

摘要翻译： 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。