公开(公告)号：US07297606B2

公开(公告)日：2007-11-20

申请号：US11116903

申请日：2005-04-28

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。 栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域 在掩埋的LDD区域中并且靠近半导体层的上表面。 第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

公开(公告)号：US20120175702A1

公开(公告)日：2012-07-12

申请号：US13428540

申请日：2012-03-23

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此间隔开。 至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。 第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

公开(公告)号：US07329922B2

公开(公告)日：2008-02-12

申请号：US10999705

申请日：2004-11-30

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7835 ,  H01L29/402 ,  H01L29/7831

摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.

摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开 。 第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。 绝缘层形成在半导体层的上表面上。 至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极 并且在第一栅极和第二源极/漏极区域之间。 第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

公开(公告)号：US07148540B2

公开(公告)日：2006-12-12

申请号：US10878857

申请日：2004-06-28

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7802 ,  H01L29/7835

摘要： An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的第二导电类型的源区和漏区，源极和漏极彼此间隔开。 在半导体层中，靠近半导体层的上表面并且在源极和漏极区之间形成漂移区，并且在漂移区的至少一部分上方的半导体层上形成绝缘层。 栅极形成在绝缘层上并且至少部分地在源极和漂移区域之间。 MOS器件还包括导电结构，该导电结构包括形成在绝缘层上并与栅极隔开的第一端，以及形成在绝缘层上并在漂移区的至少一部分上方向漏极区横向延伸的第二端。 导电结构被构造成使得当导电结构的第二端下方的绝缘层的厚度随着第二端向漏极区延伸而增加。

公开(公告)号：US07126193B2

公开(公告)日：2006-10-24

申请号：US10673539

申请日：2003-09-29

申请人： Frank A. Baiocchi ,  Bailey R. Jones ,  Muhammed Ayman Shibib ,  Shuming Xu

发明人： Frank A. Baiocchi ,  Bailey R. Jones ,  Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L31/119

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

摘要翻译： 形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及 与第一源极/漏极区域间隔开。 栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。 所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。 触点还包括直接形成在硅化物层上的至少一个绝缘层。

公开(公告)号：US07041561B2

公开(公告)日：2006-05-09

申请号：US10814062

申请日：2004-03-31

申请人： Frank A. Baiocchi ,  Bailey R. Jones ,  Muhammed Ayman Shibib ,  Shuming Xu

发明人： Frank A. Baiocchi ,  Bailey R. Jones ,  Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L29/4175

摘要： A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.

摘要翻译： 在半导体晶片中形成半导体结构的技术包括以下步骤：在第一导电类型的半导体衬底的至少一部分上形成外延层，并在半导体晶片的上表面中形成至少一个沟槽，并部分地形成 外延层。 该方法还包括在沟槽的底壁和衬底之间形成至少一个扩散区域的步骤，扩散区域在沟槽的底壁和衬底之间提供电路径。 掺杂具有已知浓度水平的第一杂质的沟槽的一个或多个侧壁，以便在外延层的上表面和至少一个扩散区之间形成电路径。 然后用填充材料填充沟槽。

公开(公告)号：US08153484B2

公开(公告)日：2012-04-10

申请号：US11999168

申请日：2007-12-04

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此间隔开。 至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。 第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

公开(公告)号：US07067890B2

公开(公告)日：2006-06-27

申请号：US10953750

申请日：2004-09-29

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/76

CPC分类号： H01L21/76208

摘要： A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.

摘要翻译： 在半导体器件中形成氧化物区域的方法包括以下步骤：在器件的半导体层中形成多个沟槽，沟槽彼此相对靠近地形成，并且氧化半导体层，使得绝缘层 形成在沟槽的至少侧壁和底壁上。 沟槽被配置成使得由氧化步骤的结果形成的绝缘层基本上填充沟槽并且基本上消耗相应的相邻的沟槽对之间的半导体层。 以这种方式，在整个多个沟槽中形成基本上连续的氧化物区域。

公开(公告)号：US06828628B2

公开(公告)日：2004-12-07

申请号：US10382142

申请日：2003-03-05

申请人： John Michael Hergenrother ,  Muhammed Ayman Shibib ,  Shuming Xu ,  Zhijian Xie

发明人： John Michael Hergenrother ,  Muhammed Ayman Shibib ,  Shuming Xu ,  Zhijian Xie

IPC分类号： H01L2972

CPC分类号： H01L29/7802 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7813 ,  H01L29/7835

摘要： A diffused MOS device comprises one or more strained silicon portions formed in a carrier transit path of the DMOS device. The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path is at least partially defined by a body of the DMOS device, and may also include other regions, such as a diffusion area, channel region, or accumulation region. The one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed as a layer throughout. The one or more strained silicon portions may be formed through patterning of a hard mask, forming a lattice mismatch layer, forming a strained silicon layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.

摘要翻译： 扩散MOS器件包括形成在DMOS器件的载流子传输路径中的一个或多个应变硅部分。 一个或多个应变硅部分可以包括通常在诸如硅锗或碳化硅的晶格失配材料层之上形成的应变硅层。 载体传输路径至少部分地由DMOS设备的主体限定，并且还可以包括诸如扩散区域，信道区域或累积区域的其他区域。 一个或多个应变硅部分可以仅形成在DMOS器件的选定区域中，或者可以形成为整个层。 可以通过图案化硬掩模，形成晶格失配层，形成应变硅层和去除硬掩模来形成一个或多个应变硅部分。 也可以在图案化的硬掩模上形成晶格失配材料之前形成沟槽。

公开(公告)号：US08648445B2

公开(公告)日：2014-02-11

申请号：US13428540

申请日：2012-03-23

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此间隔开。 至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。 第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。