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    Security systems and methods for integrated circuits
    1.
    发明授权
    Security systems and methods for integrated circuits 有权

    公开(公告)号：US11386234B2

    公开(公告)日：2022-07-12

    申请号：US16717473

    申请日：2019-12-17

    申请人： NUVOTON TECHNOLOGY CORPORATION

    发明人： Ilan Margalit

    IPC分类号： G06F21/64 ,  G06F1/24 ,  G06F21/55 ,  G11C29/04

    摘要： A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.

    System and method for coping with fault injection attacks
    2.
    发明授权
    System and method for coping with fault injection attacks 有权

    公开(公告)号：US10990682B2

    公开(公告)日：2021-04-27

    申请号：US15845412

    申请日：2017-12-18

    申请人： Nuvoton Technology Corporation

    发明人： Ilan Margalit

    IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G06F21/00 ,  G06F21/57 ,  G06F21/54 ,  G06F21/55

    摘要： A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks. Includes a processor core which, when in use, executes instructions and concurrently, generates, in real time, output indications of instructions to be executed; a fault injection detector having selectable sensitivity levels; and a sensitivity level control module operative, in real time, to receive the output indications, select a next sensitivity level using sensitivity level selection logic which receives the output indications as inputs, and set the fault injection detector to the next sensitivity level, thereby to provide fault injection countermeasure circuitry which is differentially sensitive, when protecting the processor core from fault injection attacks, depending on the output indications of the instructions, and/or avoids false alarms which would result if processor core protection were provided at a sensitivity level unrelated to the output indications of the instructions.

    Resolving automated test equipment (ATE) timing constraint violations
    3.
    发明授权
    Resolving automated test equipment (ATE) timing constraint violations 有权

    公开(公告)号：US10145893B2

    公开(公告)日：2018-12-04

    申请号：US15390505

    申请日：2016-12-25

    申请人： NUVOTON TECHNOLOGY CORPORATION

    发明人： Josef Nevo ,  Alain Bismuth ,  Ilan Margalit

    IPC分类号： G01R31/28

    摘要： A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles. The method includes scanning the received test definition, by the processor, for switch time points for which a timing of events in a first cycle immediately preceding the switch time point is different from a timing of events in a second cycle immediately following the switch time point, determining problematic switch time points for which the combined rest duration from a specific event in the first cycle to a corresponding specific event in the second cycle is shorter than a minimal switch period of the automated test equipment, changing the received test definition by extending a length of the cycles immediately preceding the determined problematic switch time points and providing the changed test definition for testing the integrated circuit device by the automated test equipment.

    Integrated circuit facilitating subsequent failure analysis and methods useful in conjunction therewith
    4.
    发明授权
    Integrated circuit facilitating subsequent failure analysis and methods useful in conjunction therewith 有权

    公开(公告)号：US11334447B2

    公开(公告)日：2022-05-17

    申请号：US17004636

    申请日：2020-08-27

    申请人： NUVOTON TECHNOLOGY CORPORATION

    发明人： Ilan Margalit

    IPC分类号： G06F11/14 ,  G06F30/32 ,  G06F115/02

    摘要： A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

    RESOLVING AUTOMATED TEST EQUIPMENT (ATE) TIMING CONSTRAINT VIOLATIONS
    7.
    发明申请
    RESOLVING AUTOMATED TEST EQUIPMENT (ATE) TIMING CONSTRAINT VIOLATIONS 审中-公开

    公开(公告)号：US20180180667A1

    公开(公告)日：2018-06-28

    申请号：US15390505

    申请日：2016-12-25

    申请人： NUVOTON TECHNOLOGY CORPORATION

    发明人： Josef Nevo ,  Alain Bismuth ,  Ilan Margalit

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2882 ,  G01R31/2834

    摘要： A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles. The method includes scanning the received test definition, by the processor, for switch time points for which a timing of events in a first cycle immediately preceding the switch time point is different from a timing of events in a second cycle immediately following the switch time point, determining problematic switch time points for which the combined rest duration from a specific event in the first cycle to a corresponding specific event in the second cycle is shorter than a minimal switch period of the automated test equipment, changing the received test definition by extending a length of the cycles immediately preceding the determined problematic switch time points and providing the changed test definition for testing the integrated circuit device by the automated test equipment.

    System and method for correction of memory errors
    8.
    发明授权
    System and method for correction of memory errors 有权

    公开(公告)号：US11475170B2

    公开(公告)日：2022-10-18

    申请号：US16423676

    申请日：2019-05-28

    申请人： NUVOTON TECHNOLOGY CORPORATION

    发明人： Ziv Hershman ,  Ilan Margalit

    IPC分类号： G06F21/00 ,  G06F21/76 ,  G06F11/10 ,  G06F21/44 ,  H04L9/32 ,  G06F9/4401 ,  G11C29/52

    摘要： A self-correcting memory system comprising an integrated circuit including memory and memory content authentication functionality, which is operative to compare content to be authenticated to a standard and to output “authentic” if the content to be authenticated equals the standard and “non-authentic” otherwise; and error correction functionality which is operative to apply at least one possible correction to at least one erroneous word entity in said memory, yielding a possibly correct word entity, call said authentication for application to the possibly correct word entity, and if the authentication's output is “authentic”, to replace said erroneous word entity in said memory, with said possibly correct word entity thereby to yield error correction at a level of confidence derived from the level of confidence associated with the authentication.