公开(公告)号：US12079097B2

公开(公告)日：2024-09-03

申请号：US17075628

申请日：2020-10-20

Applicant: NVIDIA CORPORATION

Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg

IPC: G06F11/273 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F11/2733 ,  G06F11/2268 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

公开(公告)号：US08813019B1

公开(公告)日：2014-08-19

申请号：US13873263

申请日：2013-04-30

Applicant: NVIDIA Corporation

Inventor： Avinash Rath ,  Sanjith Sleeba ,  Ashish Kumar

IPC: G06F17/50 ,  G01R31/28 ,  G01R27/28 ,  G06F11/07

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F2217/14

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

Abstract translation: 一种方法包括通过通信地耦合到存储器的计算设备的处理器读取作为其验证的一部分的电子电路的设计。 该方法还包括通过处理器提取参与验证的测试算法的一组优化的指令，使得该组优化的指令覆盖与电子电路的设计相关联的逻辑功能的最大部分。 此外，该方法包括通过处理器执行与优化的指令集相关的测试算法，以减少电子电路的设计的验证时间。

公开(公告)号：US11867744B2

公开(公告)日：2024-01-09

申请号：US17075629

申请日：2020-10-20

Applicant: NVIDIA CORPORATION

Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg ,  Sailendra Chadalavada

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F13/42

CPC classification number: G01R31/2601 ,  G01R31/2639 ,  G01R31/31725 ,  G01R31/318328 ,  G01R31/318536 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.