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公开(公告)号：US09773341B2
公开(公告)日：2017-09-26
申请号：US13971639
申请日：2013-08-20
Applicant: NVIDIA CORPORATION
Inventor： Jeffrey A. Bolz , Mark J. Kilgard
CPC classification number: G06T15/30
Abstract: One embodiment of the present invention includes techniques for rasterizing geometries. First, a processing unit defines a bounding primitive that covers the geometry and does not include any internal edges. If the bounding primitive intersects any enabled clip plane, then the processing unit generates fragments to fill a current viewport. Alternatively, the processing unit generates fragments to fill the bounding primitive. Because the rasterized region includes no internal edges, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Consequently, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with cover geometries.
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公开(公告)号：US09754561B2
公开(公告)日：2017-09-05
申请号：US14046064
申请日：2013-10-04
Applicant: NVIDIA CORPORATION
Inventor： Jonathan Dunaisky , Henry Packard Moreton , Jeffrey A. Bolz , Yury Y. Uralsky , James Leroy Deming , Rui M. Bastos , Patrick R. Brown , Amanpreet Grewal , Christian Amsinck , Poornachandra Rao , Jerome F. Duluk, Jr. , Andrew J. Tao
IPC: G06T1/60 , G06F12/08 , G06F12/10 , G09G5/39 , G06F12/0897 , G06F12/1027
CPC classification number: G09G5/39 , G06F12/0897 , G06F12/1027 , G06T1/60
Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
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公开(公告)号：US09595075B2
公开(公告)日：2017-03-14
申请号：US14038599
申请日：2013-09-26
Applicant: NVIDIA CORPORATION
Inventor： Steven J. Heinrich , Eric T. Anderson , Jeffrey A. Bolz , Jonathan Dunaisky , Ramesh Jandhyala , Joel McCormack , Alexander L. Minkin , Bryon S. Nordquist , Poornachandra Rao
CPC classification number: G06T1/60 , G06F2212/302 , G06T1/20 , G06T15/04 , G09G5/363
Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.
Abstract translation: 公开了用于在具有被配置为处理纹理存储器访问操作的第一部分的纹理处理流水线中执行存储器访问操作的方法和被配置为处理非纹理存储器访问操作的第二部分。 纹理单元接收存储器访问请求。 纹理单元确定存储器访问请求是否包括纹理存储器访问操作。 如果存储器访问请求包括纹理存储器访问操作，则纹理单元至少通过纹理处理流水线的第一部分来处理存储器访问请求，否则，纹理单元至少经由第二部分处理存储器访问请求 纹理处理流水线。 所公开方法的一个优点是可以将相同的处理和高速缓冲存储器用于纹理操作和对各种其他地址空间的加载/存储操作，导致减少的表面积和功率消耗。
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公开(公告)号：US10417990B2
公开(公告)日：2019-09-17
申请号：US14855524
申请日：2015-09-16
Applicant: Nvidia Corporation
Inventor： Jeffrey A. Bolz
Abstract: A method of binding graphics resources is provided that includes: (1) identifying graphics resources for binding, (2) generating a bind group for the graphics resources, (3) organizing the bind group into a bind group memory using a bind group layout and (4) providing bind group control for processing of the bind group. A method of organizing graphics resources and a resource organizing unit are also provided.
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公开(公告)号：US10083514B2
公开(公告)日：2018-09-25
申请号：US15289694
申请日：2016-10-10
Applicant: NVIDIA Corporation
Inventor： Mark J. Kilgard , Jeffrey A. Bolz
CPC classification number: G06T7/11 , G06T1/20 , G06T1/60 , G06T3/0012 , G06T11/40
Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
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Patent Agency Ranking
公开(公告)号：US10032242B2
公开(公告)日：2018-07-24
申请号：US14043411
申请日：2013-10-01
Applicant: NVIDIA Corporation
Inventor： Ziyad S. Hakura , Jeffrey A. Bolz , Amanpreet Grewal , Matthew Johnson , Andrei Khodakovsky
IPC: G06T1/20
Abstract: A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a flush-tiling-unit-command to a parallel processing subsystem, modifying the current set to include each render target identified in the requested set, and issuing bind-render-target commands identifying the requested set to the tile-based architecture for processing. The method further includes, if the current set of render targets includes each render target identified in the requested set, then not issuing the flush-tiling-unit-command.
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公开(公告)号：US20180165787A1
公开(公告)日：2018-06-14
申请号：US15378049
申请日：2016-12-14
Applicant: Nvidia Corporation
Inventor： Jeffrey A. Bolz
CPC classification number: G06T15/005
Abstract: A device driver is configured to identify a group of compute shaders to be executed in multiple traversals of a graphics processing pipeline. Each such compute shader accesses a compute tile of data having particular dimensions. The device driver interoperates with a tiling unit to determines dimension for a cache tile so that an integer multiple of each compute tile will fit evenly within the cache tile. Thus, when executing compute shaders in different traversals of the graphics processing pipeline, the data processed by those compute shaders can be cached in the cache tile between passes.
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公开(公告)号：US09558573B2
公开(公告)日：2017-01-31
申请号：US13717458
申请日：2012-12-17
Applicant: NVIDIA CORPORATION
Inventor： Jeffrey A. Bolz , Mark J. Kilgard
CPC classification number: G06T11/40 , G06T11/203
Abstract: A technique for efficiently rendering path images tessellates path contours into triangle tans comprising a set of representative triangles. Topology of the set of representative triangles is then optimized for greater rasterization efficiency by applying a flip operator to selected triangle pairs within the set of representative triangles. The optimized triangle pairs are then rendered using a path rendering technique, such as stencil and cover.
Abstract translation: 用于有效地渲染路径图像的技术将路径轮廓细分为三角形，包括一组代表性的三角形。 然后通过将翻转操作符应用于代表性三角形组内的选定三角形对，优化代表性三角形集合的拓扑，以实现更大的光栅化效率。 然后使用路径渲染技术（例如模版和封面）渲染优化的三角形对。
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公开(公告)号：US20140168222A1
公开(公告)日：2014-06-19
申请号：US13717458
申请日：2012-12-17
Applicant: NVIDIA CORPORATION
Inventor： Jeffrey A. Bolz , Mark J. Kilgard
IPC: G06T11/20
CPC classification number: G06T11/40 , G06T11/203
Abstract: A technique for efficiently rendering path images tessellates path contours into triangle tans comprising a set of representative triangles. Topology of the set of representative triangles is then optimized for greater rasterization efficiency by applying a flip operator to selected triangle pairs within the set of representative triangles. The optimized triangle pairs are then rendered using a path rendering technique, such as stencil and cover.
Abstract translation: 用于有效地渲染路径图像的技术将路径轮廓细分为三角形，包括一组代表性的三角形。 然后通过将翻转操作符应用于代表性三角形组内的选定三角形对，优化代表性三角形集合的拓扑，以实现更大的光栅化效率。 然后使用路径渲染技术（例如模版和封面）渲染优化的三角形对。
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公开(公告)号：US10607390B2
公开(公告)日：2020-03-31
申请号：US15378049
申请日：2016-12-14
Applicant: Nvidia Corporation
Inventor： Jeffrey A. Bolz
Abstract: A device driver is configured to identify a group of compute shaders to be executed in multiple traversals of a graphics processing pipeline. Each such compute shader accesses a compute tile of data having particular dimensions. The device driver interoperates with a tiling unit to determines dimension for a cache tile so that an integer multiple of each compute tile will fit evenly within the cache tile. Thus, when executing compute shaders in different traversals of the graphics processing pipeline, the data processed by those compute shaders can be cached in the cache tile between passes.
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