公开(公告)号：US20150028927A1

公开(公告)日：2015-01-29

申请号：US13949252

申请日：2013-07-24

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract translation: 触发器电路可以包括主锁存器和从锁存器。 每个锁存器可以具有透明模式和存储模式。 当主锁存器处于透明模式时，从锁存器可能处于存储模式; 反之亦然。 时钟信号可以通过一对时钟门控上拉晶体管和一对时钟门控的下拉晶体管来控制每个锁存器的模式，总共四个时钟门控晶体管。 时钟门控晶体管可以由主锁存器和从锁存器共享。 当共享时，可能需要更少的时钟门控晶体管，而不是被共享。 由于寄生电容的充电和放电，时钟门控晶体管可能具有寄生电容并且当经受变化的时钟信号时消耗功率。 因此，具有更少的时钟门控晶体管可以减少触发器电路消耗的功率。

公开(公告)号：US10931266B2

公开(公告)日：2021-02-23

申请号：US14456805

申请日：2014-08-11

Applicant: NVIDIA CORPORATION

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

公开(公告)号：US09667230B1

公开(公告)日：2017-05-30

申请号：US15078956

申请日：2016-03-23

Applicant: NVIDIA Corporation

Inventor： Matthew Rudolph Fojtik ,  Ilyas Elkin ,  Yanqing Zhang

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356113

Abstract: A method for operating a latch and a latch circuit are disclosed. The latch circuit comprises a storage sub-circuit, a propagation sub-circuit, and a shared clock-enabled transistor. The storage sub-circuit is configured to capture a level of an input signal when a clock signal transitions from first level to a second level and hold the captured level to generate an output signal while the clock signal is at the second level. The propagation sub-circuit is configured to enable a path through a blocking transistor to the shared clock-enabled supply node to propagate the captured level of the input signal to the storage sub-circuit. The shared clock-enabled transistor is configured to couple the shared clock-enabled supply node to a power supply while the clock signal is at the first level and decouple the shared clock-enabled supply node from the power supply while the clock signal is at the second level.

公开(公告)号：US09077329B2

公开(公告)日：2015-07-07

申请号：US14151715

申请日：2014-01-09

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  William J. Dally ,  Jonah M. Alben

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

公开(公告)号：US09071233B2

公开(公告)日：2015-06-30

申请号：US13949252

申请日：2013-07-24

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract translation: 触发器电路可以包括主锁存器和从锁存器。 每个锁存器可以具有透明模式和存储模式。 当主锁存器处于透明模式时，从锁存器可能处于存储模式; 反之亦然。 时钟信号可以通过一对时钟门控上拉晶体管和一对时钟门控的下拉晶体管来控制每个锁存器的模式，总共四个时钟门控晶体管。 时钟门控晶体管可以由主锁存器和从锁存器共享。 当共享时，可能需要更少的时钟门控晶体管，而不是被共享。 由于寄生电容的充电和放电，时钟门控晶体管可能具有寄生电容并且当经受变化的时钟信号时消耗功率。 因此，具有更少的时钟门控晶体管可以减少触发器电路消耗的功率。

公开(公告)号：US20140122949A1

公开(公告)日：2014-05-01

申请号：US13663379

申请日：2012-10-29

Applicant: NVIDIA CORPORATION

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract translation: 介绍了锁存器的系统和方法。 在一个实施例中，系统包括传播组件，数据传播组件和控制组件中的扫描。 传播分量中的扫描可操作以在数值扫描和再循环值之间进行选择。 数据传播组件可操作以在数据值和从传播组件中的扫描转发的结果之间进行选择，其中数据传播组件的结果作为再循环值被转发到传播组件中的扫描。 控制组件可操作以通过传播组件和数据传播组件中的扫描来控制选择的指示。

公开(公告)号：US20170234927A1

公开(公告)日：2017-08-17

申请号：US15257781

申请日：2016-09-06

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

公开(公告)号：US20230139623A1

公开(公告)日：2023-05-04

申请号：US17517612

申请日：2021-11-02

Applicant: NVIDIA Corporation

Inventor： Rajarshi Roy ,  Saad Godil ,  Jonathan Raiman ,  Neel Kant ,  Ilyas Elkin ,  Ming Y. Siu ,  Robert Kirby ,  Stuart Oberman ,  Bryan Catanzaro

IPC: G06F30/394 ,  G06N20/00 ,  G06F30/327

Abstract: Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.

公开(公告)号：US10120028B2

公开(公告)日：2018-11-06

申请号：US15257781

申请日：2016-09-06

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

公开(公告)号：US09438213B2

公开(公告)日：2016-09-06

申请号：US14723356

申请日：2015-05-27

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.