公开(公告)号：US12032840B2

公开(公告)日：2024-07-09

申请号：US17678784

申请日：2022-02-23

Applicant: NVIDIA CORPORATION

Inventor： Anand Shanmugam Sundararajan ,  Narayan Kulshrestha ,  Ka Yun Lee ,  Brian Smith ,  Madhukiran V. Swarna ,  Ramachandiran V ,  Kevin Wilder

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

公开(公告)号：US20240296875A1

公开(公告)日：2024-09-05

申请号：US18176836

申请日：2023-03-01

Applicant: NVIDIA Corporation

Inventor： Jason Golbus ,  Chad Parsons ,  Kirk Twardowski ,  Lalit Gupta ,  Jesse Wang ,  Ka Yun Lee ,  Amy Chen ,  Ramya Challa ,  Karan Gupta

IPC: G11C7/10 ,  G11C29/50

CPC classification number: G11C7/1048 ,  G11C7/1075 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/5004

Abstract: The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.