公开(公告)号：US12032840B2

公开(公告)日：2024-07-09

申请号：US17678784

申请日：2022-02-23

Applicant: NVIDIA CORPORATION

Inventor： Anand Shanmugam Sundararajan ,  Narayan Kulshrestha ,  Ka Yun Lee ,  Brian Smith ,  Madhukiran V. Swarna ,  Ramachandiran V ,  Kevin Wilder

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

公开(公告)号：US11487341B2

公开(公告)日：2022-11-01

申请号：US16460615

申请日：2019-07-02

Applicant: NVIDIA Corporation

Inventor： Aniket Naik ,  Tezaswi Raja ,  Kevin Wilder ,  Rajeshwaran Selvanesan ,  Divya Ramakrishnan ,  Daniel Rodriguez ,  Benjamin Faulkner ,  Raj Jayakar ,  Fei (Walter) Li

IPC: G06F1/324 ,  G06F9/38

Abstract: Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

公开(公告)号：US10444280B2

公开(公告)日：2019-10-15

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz ,  Pavan Kumar Datla Jagannadha

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/26 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

公开(公告)号：US20170115352A1

公开(公告)日：2017-04-27

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz

IPC: G01R31/317 ,  G01R31/3177

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.