公开(公告)号：US20210073042A1

公开(公告)日：2021-03-11

申请号：US16562367

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06F9/38 ,  G06F1/04 ,  G06F1/3296

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073125A1

公开(公告)日：2021-03-11

申请号：US16562361

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F12/06

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073025A1

公开(公告)日：2021-03-11

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073035A1

公开(公告)日：2021-03-11

申请号：US16562364

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/38

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20170161206A1

公开(公告)日：2017-06-08

申请号：US15437400

申请日：2017-02-20

Applicant: NVIDIA Corporation

Inventor： James Leroy DEMING ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsey EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06F12/1027 ,  G06F9/46

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.