公开(公告)号：US20210073042A1

公开(公告)日：2021-03-11

申请号：US16562367

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06F9/38 ,  G06F1/04 ,  G06F1/3296

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20140281263A1

公开(公告)日：2014-09-18

申请号：US14109678

申请日：2013-12-17

Applicant: NVIDIA CORPORATION

Inventor： James Leroy DEMING ,  Jerome F. DULUK, Jr. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsay EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

Abstract translation: 本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。 当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。 重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。 当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。 有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

公开(公告)号：US20230409486A1

公开(公告)日：2023-12-21

申请号：US18456420

申请日：2023-08-25

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/1009 ,  G06F11/07 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F12/10

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20210073125A1

公开(公告)日：2021-03-11

申请号：US16562361

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F12/06

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073025A1

公开(公告)日：2021-03-11

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20220405211A1

公开(公告)日：2022-12-22

申请号：US17820870

申请日：2022-08-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  Josh MASHEY

IPC: G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/08 ,  G06F11/07 ,  G06F12/12

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20170286198A9

公开(公告)日：2017-10-05

申请号：US14055345

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F11/07 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20170249254A9

公开(公告)日：2017-08-31

申请号：US14055367

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20170185526A9

公开(公告)日：2017-06-29

申请号：US14055382

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US20170329717A9

公开(公告)日：2017-11-16

申请号：US14055356

申请日：2013-10-16

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/1009 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/12 ,  G06F11/07

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.