公开(公告)号：US11967396B2

公开(公告)日：2024-04-23

申请号：US17730401

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Jaewon Lee

IPC分类号： G11C7/10 ,  G11C7/14

CPC分类号： G11C7/1066 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/14

摘要： A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

公开(公告)号：US20230352067A1

公开(公告)日：2023-11-02

申请号：US17730401

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Jaewon Lee

IPC分类号： G11C7/10 ,  G11C7/14

CPC分类号： G11C7/1066 ,  G11C7/1093 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/14

摘要： A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

公开(公告)号：US20240235557A1

公开(公告)日：2024-07-11

申请号：US18614490

申请日：2024-03-22

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17784

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US11881255B2

公开(公告)日：2024-01-23

申请号：US17730379

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Abhishek Dhir ,  Michael Ivan Halfen ,  Chunjen Su

IPC分类号： G11C11/40 ,  G11C11/4093 ,  H03K17/687

CPC分类号： G11C11/4093 ,  H03K17/6874

摘要： A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

公开(公告)号：US20230352081A1

公开(公告)日：2023-11-02

申请号：US17730379

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Abhishek Dhir ,  Michael Ivan Halfen ,  CHUNJEN SU

IPC分类号： G11C11/4093 ,  H03K17/687

CPC分类号： G11C11/4093 ,  H03K17/6874

摘要： A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

公开(公告)号：US20230352078A1

公开(公告)日：2023-11-02

申请号：US17730423

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Hsuche Nee ,  Po-Chien Chiang

IPC分类号： G11C11/4074

CPC分类号： G11C11/4074

摘要： The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.

公开(公告)号：US11973501B2

公开(公告)日：2024-04-30

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17784

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US20230353155A1

公开(公告)日：2023-11-02

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17736

CPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17744 ,  H03K19/1774

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US11978496B2

公开(公告)日：2024-05-07

申请号：US17730333

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Po-Chien Chiang ,  Hsuche Nee ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： G11C11/4074

CPC分类号： G11C11/4074

摘要： A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

公开(公告)号：US20230352077A1

公开(公告)日：2023-11-02

申请号：US17730333

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Po-Chien Chiang ,  Hsuche Nee ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： G11C11/4074

CPC分类号： G11C11/4074

摘要： A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.