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    TECHNIQUES FOR ACCESSING AND UTILIZING COMPRESSED DATA AND ITS STATE INFORMATION
    1.
    发明申请
    TECHNIQUES FOR ACCESSING AND UTILIZING COMPRESSED DATA AND ITS STATE INFORMATION 有权

    公开(公告)号：US20210373774A1

    公开(公告)日：2021-12-02

    申请号：US16888116

    申请日：2020-05-29

    Applicant: NVIDIA Corporation

    Inventor： Ram Rangan ,  Patrick Richard Brown ,  Wishwesh Anil Gandhi ,  Steven James Heinrich ,  Mathias Heyer ,  Emmett Michael Kilgariff ,  Praveen Krishnamurthy ,  Dong Han Ryu

    IPC: G06F3/06 ,  H03M7/30

    Abstract: Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.

    TECHNIQUES FOR DYNAMICALLY COMPRESSING MEMORY REGIONS HAVING A UNIFORM VALUE
    2.
    发明申请
    TECHNIQUES FOR DYNAMICALLY COMPRESSING MEMORY REGIONS HAVING A UNIFORM VALUE 有权

    公开(公告)号：US20210349639A1

    公开(公告)日：2021-11-11

    申请号：US16866813

    申请日：2020-05-05

    Applicant: NVIDIA Corporation

    Inventor： Ram Rangan ,  Suryakant Patidar ,  Praveen Krishnamurthy ,  Wishwesh Anil Gandhi

    IPC: G06F3/06 ,  H03M7/30

    Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

    Techniques for dynamically compressing memory regions having a uniform value
    3.
    发明授权
    Techniques for dynamically compressing memory regions having a uniform value 有权

    公开(公告)号：US11513686B2

    公开(公告)日：2022-11-29

    申请号：US16866813

    申请日：2020-05-05

    Applicant: NVIDIA Corporation

    Inventor： Ram Rangan ,  Suryakant Patidar ,  Praveen Krishnamurthy ,  Wishwesh Anil Gandhi

    IPC: G06F3/06 ,  H03M7/30

    Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

    Techniques for efficiently organizing and accessing compressible data
    4.
    发明授权
    Techniques for efficiently organizing and accessing compressible data 有权

    公开(公告)号：US11061571B1

    公开(公告)日：2021-07-13

    申请号：US16824527

    申请日：2020-03-19

    Applicant: NVIDIA CORPORATION

    Inventor： Praveen Krishnamurthy ,  Wishwesh Anil Gandhi

    IPC: G06F3/06

    Abstract: In various embodiments, a memory interface unit organizes data within a memory tile to facilitate efficient memory accesses. In an embodiment, a memory tile represents a portion of memory that holds multiple chunks of data, where each chunk is stored either in a non-compressed or in a smaller compressed data format. In an embodiment, the tile is organized to pack multiple compressed chunks together so that multiple compressed chunks can be retrieved from memory with a single read access. In another embodiment, the tile is organized to store redundant copies of compressed chunks so that a compressed chunk can be quickly decompressed within a tile without having to relocate other compressed chunks in the tile. Additional embodiments are further disclosed for allowing efficient accesses to both compressed and non-compressed data.

    TECHNIQUES FOR SCALING DICTIONARY-BASED COMPRESSION
    6.
    发明申请
    TECHNIQUES FOR SCALING DICTIONARY-BASED COMPRESSION 有权

    公开(公告)号：US20210349761A1

    公开(公告)日：2021-11-11

    申请号：US16866811

    申请日：2020-05-05

    Applicant: NVIDIA Corporation

    Inventor： Ram Rangan ,  Suryakant Patidar ,  Praveen Krishnamurthy ,  Wishwesh Anil Gandhi

    IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02

    Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

    Architecture and algorithms for data compression
    7.
    发明授权
    Architecture and algorithms for data compression 有权

    公开(公告)号：US10338820B2

    公开(公告)日：2019-07-02

    申请号：US15176082

    申请日：2016-06-07

    Applicant: NVIDIA Corporation

    Inventor： Rouslan Dimitrov ,  Jeff Pool ,  Praveen Krishnamurthy ,  Chris Amsinck ,  Karan Mehra ,  Scott Cutler

    IPC: H03M7/00 ,  G06F3/06 ,  H03M7/30 ,  G06T1/20 ,  H03M7/40

    Abstract: A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.

    Techniques for scaling dictionary-based compression
    9.
    发明授权
    Techniques for scaling dictionary-based compression 有权

    公开(公告)号：US11263051B2

    公开(公告)日：2022-03-01

    申请号：US16866811

    申请日：2020-05-05

    Applicant: NVIDIA Corporation

    Inventor： Ram Rangan ,  Suryakant Patidar ,  Praveen Krishnamurthy ,  Wishwesh Anil Gandhi

    IPC: G06F9/50 ,  G06F9/30 ,  G06F12/02 ,  G06F9/38 ,  H03M7/30 ,  H03M7/42

    Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

    Organizing memory to optimize memory accesses of compressed data
    10.
    发明授权
    Organizing memory to optimize memory accesses of compressed data 有权

    公开(公告)号：US10402323B2

    公开(公告)日：2019-09-03

    申请号：US14925920

    申请日：2015-10-28

    Applicant: NVIDIA CORPORATION

    Inventor： Praveen Krishnamurthy ,  Peter B. Holmquist ,  Wishwesh Gandhi ,  Timothy Purcell ,  Karan Mehra ,  Lacky Shah

    IPC: G06F12/08 ,  G06F12/0802 ,  G06F3/06

    Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.

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