公开(公告)号：US11893653B2

公开(公告)日：2024-02-06

申请号：US16408173

申请日：2019-05-09

Applicant: Nvidia Corporation

Inventor： Amit Rao ,  Ashish Srivastava ,  Yogesh Kini

IPC: G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/5016 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

公开(公告)号：US20240232050A1

公开(公告)日：2024-07-11

申请号：US18152666

申请日：2023-01-10

Applicant: NVIDIA Corporation

Inventor： Saumya Nair ,  Yogesh Kini ,  Ashutosh Jain ,  Neeraja Gubba

IPC: G06F11/36

CPC classification number: G06F11/3644 ,  G06F11/3664 ,  G06F11/3688

Abstract: One or more embodiments of the present disclosure relate to executing a software testing tool to identify function calls—internal and/or external—of software code and their corresponding errors. Once identified—such as during an information gathering operation—the error codes may be returned in place of actual outputs of the function during testing, and the downstream processing of the software as a result of the errors may be evaluated. As such, an automatic software testing tool may be implemented that not only identifies functions calls and corresponding errors, but also evaluates performance of the software in view of the various different error types associated with the function calls.

公开(公告)号：US20230083345A1

公开(公告)日：2023-03-16

申请号：US17468128

申请日：2021-09-07

Applicant: NVIDIA Corporation

Inventor： Ashok Kelur ,  Rahul Suresh ,  Yogesh Kini ,  Karthik Raghavan Ravi ,  Neeraja Gubba ,  Priyal Rathi

IPC: G06N5/04 ,  G06N3/08 ,  G06N3/04 ,  G06F9/54

Abstract: Apparatuses, systems, and techniques to perform multi-architecture execution graphs. In at least one embodiment, a parallel processing platform, such as compute uniform device architecture (CUDA) generates multi-architecture execution graphs comprising a plurality of software kernels to be performed by one or more processor cores having one or more processor architectures.

公开(公告)号：US12236218B2

公开(公告)日：2025-02-25

申请号：US17879447

申请日：2022-08-02

Applicant: NVIDIA Corporation

Inventor： Ashutosh Jain ,  Charan Pai ,  Deepak Ravi ,  Karthik Raghavan Ravi ,  Kiran Sj ,  Yogesh Kini

IPC: G06F8/41

Abstract: In various examples, techniques for performing software code verification are described. Systems and methods are disclosed for generating, using intermediate code and user input, a call graph that represents source code for software. For instance, the call graph represents at least functions (e.g., internal functions, external functions, etc.) associated with the software, calls (e.g., direct calls, call pointers, etc.) between the functions, and register information associated with the functions (e.g., variables used by the functions, assembly code used by the functions, etc.). The systems and methods may further use the call graph to perform software code verification by verifying rules from design specifications for the software and/or rules from various certification standards.

公开(公告)号：US20190266695A1

公开(公告)日：2019-08-29

申请号：US16408173

申请日：2019-05-09

Applicant: Nvidia Corporation

Inventor： Amit Rao ,  Ashish Srivastava ,  Yogesh Kini

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

公开(公告)号：US10319060B2

公开(公告)日：2019-06-11

申请号：US14601223

申请日：2015-01-20

Applicant: Nvidia Corporation

Inventor： Amit Rao ,  Ashish Srivastava ,  Yogesh Kini

IPC: G06F13/14 ,  G06T1/20 ,  G06F12/109 ,  G06T1/60 ,  G06F9/50

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

公开(公告)号：US20250138884A1

公开(公告)日：2025-05-01

申请号：US19006732

申请日：2024-12-31

Applicant: NVIDIA Corporation

Inventor： Sharan Ashwathnarayan ,  Debalina Bhattacharjee ,  Ashok Kelur ,  Alok Parikh ,  Yogesh Kini ,  Amit Rao ,  Aingarathasan Paramakuru ,  Kathleen E. Danielson ,  Daniel Jonathan Hettena ,  Vladislav Buzov

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/52

Abstract: Apparatus, systems, and techniques to share memory. In at least one embodiment, a processor comprises one or more circuits to allocate memory to at least two heterogeneous processing cores in response to performing one or more instructions associated with one or more application programming interfaces based, at least in part, on one or more attributes associated with the at least two heterogeneous processing cores.

公开(公告)号：US12265463B2

公开(公告)日：2025-04-01

申请号：US18152666

申请日：2023-01-10

Applicant: NVIDIA Corporation

Inventor： Saumya Nair ,  Yogesh Kini ,  Ashutosh Jain ,  Neeraja Gubba

IPC: G06F11/32 ,  G06F9/54 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3668 ,  G06F11/07 ,  G06F11/22 ,  G06F11/263 ,  G06F11/34

Abstract: One or more embodiments relate to executing a software testing tool to identify function calls—internal and/or external—of software code and their corresponding errors. Once identified-such as during an information gathering operation-the error codes may be returned in place of actual outputs of the function during testing, and the downstream processing of the software as a result of the errors may be evaluated. As such, an automatic software testing tool may be implemented that not only identifies functions calls and corresponding errors, but also evaluates performance of the software in view of the various different error types associated with the function calls.

公开(公告)号：US20240045662A1

公开(公告)日：2024-02-08

申请号：US17879447

申请日：2022-08-02

Applicant: NVIDIA Corporation

Inventor： Ashutosh Jain ,  Charan Pai ,  Deepak Ravi ,  Karthik Raghavan Ravi ,  Kiran SJ ,  Yogesh Kini

IPC: G06F8/41

CPC classification number: G06F8/434

Abstract: In various examples, techniques for performing software code verification are described. Systems and methods are disclosed for generating, using intermediate code and user input, a call graph that represents source code for software. For instance, the call graph represents at least functions (e.g., internal functions, external functions, etc.) associated with the software, calls (e.g., direct calls, call pointers, etc.) between the functions, and register information associated with the functions (e.g., variables used by the functions, assembly code used by the functions, etc.). The systems and methods may further use the call graph to perform software code verification by verifying rules from design specifications for the software and/or rules from various certification standards.