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公开(公告)号：US20180343013A1
公开(公告)日：2018-11-29
申请号：US15926442
申请日：2018-03-20
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.
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2.发明申请公开(公告)号：US20220239311A1
公开(公告)日：2022-07-28
申请号：US17158857
申请日：2021-01-26
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.
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公开(公告)号：US20190245553A1
公开(公告)日：2019-08-08
申请号：US15935045
申请日：2018-03-25
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.
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4.发明申请公开(公告)号：US20220239314A1
公开(公告)日：2022-07-28
申请号：US17158913
申请日：2021-01-26
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.
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公开(公告)号：US20180183459A1
公开(公告)日：2018-06-28
申请号：US15849672
申请日：2017-12-21
申请人： NXP B.V.
IPC分类号： H03M3/00
CPC分类号： H03M3/352 , H03M1/0863 , H03M1/12 , H03M3/344 , H03M3/376 , H03M3/412 , H03M3/458 , H03M3/464
摘要： A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.
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公开(公告)号：US20170019124A1
公开(公告)日：2017-01-19
申请号：US15197398
申请日：2016-06-29
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
摘要翻译： 一种Σ-Δ调制器，包括彼此串联的多个滤波器级，其中所述多个滤波器级中的至少一个被配置为提供滤波器输出信号; 以及多个增益级，每个增益级被配置为提供增益输出信号。 Σ-Δ调制器还包括滤波器输出开关元件，其被配置为选择性地将滤波器输出信号耦合到多个增益级之一的输入端; 和多个滤波器输入开关元件。 多个滤波器输入开关元件中的每一个与多个滤波器级中的一个相关联，其中多个滤波器输入开关元件被配置为选择性地将增益级输出信号之一耦合到 其相关联的一个滤波器级的输入端。
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