公开(公告)号：US08988264B2

公开(公告)日：2015-03-24

申请号：US13780679

申请日：2013-02-28

Applicant: NXP B.V.

Inventor： Kyoohyun Noh ,  Jose de Jesus Pineda De Gyvez ,  Maarten Vertregt

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/60 ,  H03M1/06

CPC classification number: H03M1/002 ,  H03M1/0682 ,  H03M1/1215 ,  H03M1/60

Abstract: An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

Abstract translation: 具有门控电压控制振荡器（GRVCO）的模数转换器（ADC），用于根据输入电压产生相位信号; 以及用于产生量化相位输出信号的量化电路。 GRVCO根据门控控制信号在第一或第二工作模式下工作。 在第一种操作模式下，GRVCO在禁止门禁的VCO模式下工作。 在第二种操作模式中，GRVCO在GRVCO模式下工作，其中根据门控信号启用或禁用门控。

公开(公告)号：US10819331B1

公开(公告)日：2020-10-27

申请号：US16404931

申请日：2019-05-07

Applicant: NXP B.V.

Inventor： Sebastien Antonius Josephus Fabrie ,  Maarten Vertregt ,  Ajay Kapoor

IPC: H03K17/687 ,  H03K17/14 ,  H03K17/16

Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.