公开(公告)号：US09866206B2

公开(公告)日：2018-01-09

申请号：US15186408

申请日：2016-06-17

Applicant: NXP B.V.

Inventor： Maurits Storms ,  Soenke Ostertun ,  Frantisek Cevela

IPC: G11C16/08 ,  H03K3/356 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26 ,  H02M3/07 ,  G11C5/14 ,  G11C8/08

CPC classification number: H03K3/356182 ,  G11C5/14 ,  G11C5/147 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H02M3/07 ,  H03K3/35613

Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.

公开(公告)号：US20160373092A1

公开(公告)日：2016-12-22

申请号：US15186408

申请日：2016-06-17

Applicant: NXP B.V.

Inventor： Maurits Storms ,  Soenke Ostertun ,  Frantisek Cevela

IPC: H03K3/356 ,  G11C16/26 ,  G11C16/08 ,  H02M3/07 ,  G11C16/10

CPC classification number: H03K3/356182 ,  G11C5/14 ,  G11C5/147 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H02M3/07 ,  H03K3/35613

Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.