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    Memory cell bit valve loss detection and restoration
    1.
    发明授权
    Memory cell bit valve loss detection and restoration 有权
    存储单元位阀失效检测和恢复

    公开(公告)号：US07653846B2

    公开(公告)日：2010-01-26

    申请号：US11648490

    申请日：2006-12-28

    申请人： Nam Sung Kim ,  Muhammad Kheliah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    发明人： Nam Sung Kim ,  Muhammad Kheliah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    IPC分类号： G11C29/00

    CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C29/38 ,  G11C29/50 ,  G11C2029/0409

    摘要： For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.

    摘要翻译： 对于一个实施例，装置可以包括存储单元以存储位值，其中存储单元可能会响应于存储器访问操作而丢失位值。 该装置还可以包括第一电路，用于响应于检测到存储器单元丢失比特值来检测存储器单元是否响应于存储器访问操作而丢失位值以及第二电路来恢复存储器单元中的位值。 其他实施例包括其他装置，方法和系统。

    Memory having bit line with resistor(s) between memory cells
    8.
    发明授权
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US07558097B2

    公开(公告)日：2009-07-07

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。

    Memory cell bit valve loss detection and restoration
    9.
    发明申请
    Memory cell bit valve loss detection and restoration 有权
    存储单元位阀失效检测和恢复

    公开(公告)号：US20080162986A1

    公开(公告)日：2008-07-03

    申请号：US11648490

    申请日：2006-12-28

    申请人： Nam Sung Kim ,  Muhammad Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    发明人： Nam Sung Kim ,  Muhammad Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    IPC分类号： G06F11/00

    CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C29/38 ,  G11C29/50 ,  G11C2029/0409

    摘要： For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.

    摘要翻译： 对于一个所公开的实施例，装置可以包括存储单元以存储位值，其中存储单元可以响应于存储器访问操作而丢失位值。 该装置还可以包括第一电路，用于响应于存储器单元丢失比特值的检测，检测存储器单元是否响应于存储器访问操作而丢失比特值以及第二电路来恢复存储器单元中的比特值。 还公开了其他实施例。

    Memory having bit line with resistor(s) between memory cells
    10.
    发明申请
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US20080158932A1

    公开(公告)日：2008-07-03

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。