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    Memory having bit line with resistor(s) between memory cells
    1.
    发明授权
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US07558097B2

    公开(公告)日：2009-07-07

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。

    Memory having bit line with resistor(s) between memory cells
    2.
    发明申请
    Memory having bit line with resistor(s) between memory cells 有权
    存储器与存储器单元之间的电阻器具有位线

    公开(公告)号：US20080158932A1

    公开(公告)日：2008-07-03

    申请号：US11648399

    申请日：2006-12-28

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。 存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。 沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。 访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。 还公开了其他实施例。

    Memory driver circuits with embedded level shifters
    4.
    发明申请
    Memory driver circuits with embedded level shifters 审中-公开
    具有嵌入式电平转换器的存储器驱动器电路

    公开(公告)号：US20080080266A1

    公开(公告)日：2008-04-03

    申请号：US11527782

    申请日：2006-09-27

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek K. De

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek K. De

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C8/08

    摘要： A memory line driver system may include a first input line to receive a clock-gated signal associated with a first supply power level, a second input line to receive an information signal associated with a second supply power level, and an output to drive a memory cell line according to the first supply power level based on the clock-gated signal and the information signal.

    摘要翻译： 存储器线路驱动器系统可以包括用于接收与第一电源功率电平相关联的时钟门控信号的第一输入线，用于接收与第二电源电平相关联的信息信号的第二输入线以及驱动存储器的输出 基于时钟门控信号和信息信号，根据第一供电功率电平进行单元线路的连接。

    Memory cell having p-type pass device
    5.
    发明授权
    Memory cell having p-type pass device 有权
    具有p型通过装置的存储单元

    公开(公告)号：US07230842B2

    公开(公告)日：2007-06-12

    申请号：US11225912

    申请日：2005-09-13

    申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Nam Sung Kim ,  Yibin Ye ,  Vivek K. De ,  Kevin Zhang ,  Bo Zheng

    发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Nam Sung Kim ,  Yibin Ye ,  Vivek K. De ,  Kevin Zhang ,  Bo Zheng

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  Y10S257/903

    摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，一种装置包括耦合在单元电压节点和存储节点之间的第一p型装置，耦合在存储节点和参考电压节点之间的n型装置和耦合在第二p型装置之间 存储节点响应于选择线上的信号到位线。 衬底中的形成第一p型器件和第二p型器件的扩散区域的至少一侧基本对齐。 还公开了其他实施例。

    SENSE AMPLIFIER METHOD AND ARRANGEMENT
    6.
    发明申请
    SENSE AMPLIFIER METHOD AND ARRANGEMENT 有权
    SENSE放大器方法和布置

    公开(公告)号：US20090003108A1

    公开(公告)日：2009-01-01

    申请号：US11772151

    申请日：2007-06-30

    申请人： Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Nam Sung Kim ,  Vivek K. De

    发明人： Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Nam Sung Kim ,  Vivek K. De

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/005

    摘要： In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.

    摘要翻译： 在一个实施例中，公开了一种具有用于读出放大器的可选配置的存储器系统。 存储器系统可以包括位单元和耦合到位单元和读出放大器的第一部分的开关模块。 开关模块可以基于对读出放大器的第一部分的输入偏移电压的测试来连接，断开或将该位单元交叉耦合到读出放大器。 类似的配置可以由读出放大器的第二部分来实现。 该系统还可以包括用于配置开关模块的设置的编程器模块，并且可以包括列选择模块，以便基于要读取的位单元的列来将位单元耦合到读出放大器。 还公开了其他实施例。

    Method and apparatus for leakage compensation with full Vcc pre-charge
    7.
    发明授权
    Method and apparatus for leakage compensation with full Vcc pre-charge 有权
    具有全Vcc预充电的漏电补偿方法和装置

    公开(公告)号：US06801463B2

    公开(公告)日：2004-10-05

    申请号：US10273627

    申请日：2002-10-17

    申请人： Muhammad M. Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    发明人： Muhammad M. Khellah ,  Yibin Ye ,  Dinesh Somasekhar ,  Vivek De

    IPC分类号： G11C700

    CPC分类号： G11C7/12

    摘要： A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.

    摘要翻译： 一种允许全VCC预充电的漏电补偿方式。 存储器单元阵列耦合在一对位线之间。 预充电电路将该对位线预充电到基本上的电源电压电平，并且泄漏补偿电路向位线中的第一位提供第一补偿电流，以在存储器访问操作期间基本上补偿由第一位线提供的泄漏电流 指向多个存储器单元中的一个。

    Dual gate oxide one time programmable (OTP) antifuse cell
    8.
    发明授权
    Dual gate oxide one time programmable (OTP) antifuse cell 有权
    双栅氧化层一次可编程（OTP）反熔丝

    公开(公告)号：US07280425B2

    公开(公告)日：2007-10-09

    申请号：US11239903

    申请日：2005-09-30

    申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

    摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

    摘要翻译： 一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物 存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

    OTP antifuse cell and cell array
    9.
    发明授权
    OTP antifuse cell and cell array 有权
    OTP反熔丝电池和电池阵列

    公开(公告)号：US07102951B2

    公开(公告)日：2006-09-05

    申请号：US10979605

    申请日：2004-11-01

    申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

    摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

    摘要翻译： 包括一次性可编程反熔丝电池的不同实施例。 在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。 反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。 感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。 高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。