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1.发明授权公开(公告)号：US08484528B2
公开(公告)日：2013-07-09
申请号：US12783120
申请日：2010-05-19
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1128 , H03M13/1165 , H03M13/3715 , H03M13/6502
摘要： Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.
摘要翻译： 本文公开了一种接收装置，包括：解码部分，被配置为接收和解码低密度奇偶校验码; 以及解码控制部分，被配置为基于作为指示在解码部分中影响功耗的通信条件的索引的条件信息来控制解码的频率。
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2.发明授权公开(公告)号：US08464124B2
公开(公告)日：2013-06-11
申请号：US12783291
申请日：2010-05-19
IPC分类号： H03M13/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/3715 , H03M13/6552 , H04L1/0053 , H04L1/0057
摘要： A receiving apparatus receives a low density parity check (“LCPC”) code and decode the LCPC code to provide for error check capabilities. A bit error rate (“BER”) controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.
摘要翻译： 接收装置接收低密度奇偶校验（“LCPC”）码并解码LCPC码以提供错误检查能力。 差错率（“BER”）控制部分是通过使用由BER条件信息组成的索引来指示LCPC的频率，该条件信息指示在解码时影响功耗的通信条件。 基于低密度奇偶校验码的接收间隔来控制频率。
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3.发明申请公开(公告)号：US20100306615A1
公开(公告)日：2010-12-02
申请号：US12783120
申请日：2010-05-19
CPC分类号： H03M13/1111 , H03M13/1128 , H03M13/1165 , H03M13/3715 , H03M13/6502
摘要： Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode an low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.
摘要翻译： 这里公开了一种接收装置，包括：解码部分，被配置为接收和解码低密度奇偶校验码; 以及解码控制部分，被配置为基于作为指示在解码部分中影响功耗的通信条件的索引的条件信息来控制解码的频率。
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公开(公告)号：US08401126B2
公开(公告)日：2013-03-19
申请号：US11473126
申请日：2006-06-23
IPC分类号： H04B1/66
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.
摘要翻译： 本发明可以减少跟踪时的功耗。 本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元 其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元， 路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域 对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域 在各个时间点读取数据，以停止从指定的子区域读取数据。
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公开(公告)号：US20070104296A1
公开(公告)日：2007-05-10
申请号：US11473126
申请日：2006-06-23
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.
摘要翻译： 本发明可以减少跟踪时的功耗。 本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元 其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元， 路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域 对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域 在各个时间点读取数据，以停止从指定的子区域读取数据。
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公开(公告)号：US08938002B2
公开(公告)日：2015-01-20
申请号：US13380758
申请日：2010-06-23
IPC分类号： G06F12/00 , H04N7/173 , H04H40/90 , H04H60/11 , H04N7/167 , H04N21/434 , H04N21/438 , H04N21/44
CPC分类号： H04N7/173 , H04H40/90 , H04H60/11 , H04N7/167 , H04N21/4347 , H04N21/4383 , H04N21/44004
摘要： A data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. A read/write control portion executes read/write control in which slots subject to extraction of two or more slots in one frame that is a collection of two or more slots each of which is a unit of error correction coding are written to a ring buffer and the slots subject to extraction in one frame written to the ring buffer are read within the unit time. When slots subject to extraction are changed, an output portion executes output processing in which dummy data outputted from a dummy data output portion are outputted with a timing immediately before a change start frame that is a frame from which the change of slots subject to extraction is started and, slots subject to extraction read from the ring buffer are outputted for frames subsequent to the change start frame. The present disclosure is applicable to reception apparatuses for receiving BS digital broadcasting, for example.
摘要翻译： 一种数据处理装置，数据处理方法和程序，被配置为防止（或降低）装置的规模和成本的增加。 读/写控制部分执行读/写控制，其中在一帧中作为两个或更多个时隙的集合的两个或更多个时隙中的两个或更多个时隙被提取的时隙，每个时隙都是纠错编码的单位，被写入环形缓冲器 并且在单位时间内读取在写入环形缓冲器的一帧中被提取的时隙。 当进行提取的时隙发生改变时，输出部分执行输出处理，其中从伪数据输出部分输出的虚拟数据以紧邻改变开始帧之前的定时被输出，该改变开始帧是从其提取的时隙的改变是 开始，并且从改变开始帧之后的帧输出从环形缓冲器读取的提取的时隙。 例如，本公开可应用于接收BS数字广播的接收装置。
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公开(公告)号：US08547970B2
公开(公告)日：2013-10-01
申请号：US13185710
申请日：2011-07-19
IPC分类号： H04J3/04
CPC分类号： H04N21/4345 , H04N21/4347 , H04N21/4382 , H04N21/4385
摘要： The present disclosure provides a receiver including a demodulation circuit adapted to demodulate data and control information attached to the data, and an extraction circuit adapted to extract some data from entire control information, wherein the demodulation circuit performs demodulation according to the extracted some data.
摘要翻译： 本公开提供了一种接收机，包括：解调电路，用于解调附加到数据的数据和控制信息;以及提取电路，适于从整个控制信息中提取一些数据，其中解调电路根据提取的一些数据进行解调。
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公开(公告)号：US08385371B2
公开(公告)日：2013-02-26
申请号：US12597527
申请日：2008-04-25
申请人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
发明人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
IPC分类号： H04J3/06
CPC分类号： H04L7/08 , H04H20/74 , H04H40/90 , H04L27/2656 , H04L27/2675
摘要： A frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths. A differential correlation detector calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. Frame period confirmation counters perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 1 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.
摘要翻译： 一种帧同步器，帧同步方法和解调器，其可以更可靠地建立可能具有多个帧长度的输入信号的帧同步。 差分相关检测器计算与无输入信号中插入的导频信号不相关的导频的差分相关值，以及与插入在输入信号中的导频信号的存在相关联的导频的差分相关值 。 帧周期确认计数器基于不具有导频的差分相关值，分别对帧长度为21690和32490个符号的输入信号进行适合的帧同步控制。 帧周期确认计数器1基于与分别具有帧长度为22194和33282个符号的输入信号相适应的具有导频的差分相关值来执行帧同步控制。
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公开(公告)号：US20100135335A1
公开(公告)日：2010-06-03
申请号：US12597527
申请日：2008-04-25
申请人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
发明人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
IPC分类号： H04J3/06
CPC分类号： H04L7/08 , H04H20/74 , H04H40/90 , H04L27/2656 , H04L27/2675
摘要： The present invention relates to a frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths.A differential correlation detector 151 calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. The frame period confirmation counters 152-1 and 152-3 perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 152-2 and 152-4 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.The present invention is applicable, for example, to a satellite broadcast receiver.
摘要翻译： 帧同步器，帧同步方法和解调器技术领域本发明涉及帧同步器，帧同步方法和解调器，其可以更可靠地建立可能具有多个帧长度的输入信号的帧同步。 差分相关检测器151计算与没有插入在输入信号中的导频信号不相关的导频的差分相关值以及与插入在输入端中的导频信号的存在相关联的导频的差分相关值 信号。 帧周期确认计数器152-1,152-3分别基于不具有导频的差分相关值，分别对帧长度分别为21690和32490的输入信号进行适合的帧同步控制。 帧周期确认计数器152-2,152-4分别基于具有导频的差分相关值，分别对帧长度为22194和33282符号的输入信号进行适合的帧同步控制。 本发明可以应用于例如卫星广播接收机。
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公开(公告)号：US20120110284A1
公开(公告)日：2012-05-03
申请号：US13380758
申请日：2010-06-23
IPC分类号： G06F12/00
CPC分类号： H04N7/173 , H04H40/90 , H04H60/11 , H04N7/167 , H04N21/4347 , H04N21/4383 , H04N21/44004
摘要： The present invention relates to a data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus.A read/write control portion 73 executes read/write control in which slots subject to extraction of two or more slots in one frame that is a collection of two or more slots each of which is a unit of error correction coding are written to a ring buffer 71 and the slots subject to extraction in one frame written to the ring buffer 71 are read within the unit time. When slots subject to extraction are changed, an output portion 76 executes output processing in which dummy data outputted from a dummy data output portion 75 are outputted with a timing immediately before a change start frame that is a frame from which the change of slots subject to extraction is started and, slots subject to extraction read from the ring buffer 71 are outputted for frames subsequent to the change start frame. The present invention is applicable to reception apparatuses for receiving BS digital broadcasting, for example.
摘要翻译： 本发明涉及一种数据处理装置，数据处理方法和程序，其被配置为防止（或降低）装置的规模和成本的增加。 读/写控制部分73执行读/写控制，其中在作为两个或更多个时隙的两个或多个时隙的集合中的两个或更多个时隙的一个帧中的两个或更多个时隙作为纠错编码的单位被提取的时隙写入环 在单位时间内读取缓冲器71，并且在写入环形缓冲器71的一帧中进行提取的时隙。 当进行提取的时隙发生改变时，输出部分76执行输出处理，其中从伪数据输出部分75输出的虚拟数据以紧接改变开始帧之前的定时被输出 提取开始，并且从改变开始帧之后的帧输出从环形缓冲器71读取的提取的时隙。 本发明例如适用于接收BS数字广播的接收装置。
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