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公开(公告)号：US20100031269A1
公开(公告)日：2010-02-04
申请号：US12181811
申请日：2008-07-29
申请人： Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker , Mark Wayne VanderWiele
发明人： Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker , Mark Wayne VanderWiele
IPC分类号： G06F9/46
摘要： Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.
摘要翻译： 说明性实施例提供了一种计算机实现的方法，数据处理系统和用于锁定争用减少的计算机程序产品。 在一个示例性实施例中，计算机实现的方法向活动线程提供锁定，增加锁定计数器，接收去调度活动线程的请求，并且确定锁是否被活动线程保持。 计算机实现的方法响应于锁定被活动线程保持的确定，将第一预定量添加到活动线程的时间片。
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2.发明授权Reducing lock contention by adding a time slice to an active thread holding a lock 有权通过向持有锁定的活动线程添加时间片来减少锁争用公开(公告)号：US08166480B2
公开(公告)日：2012-04-24
申请号：US12181811
申请日：2008-07-29
申请人： Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker , Mark Wayne VanderWiele
发明人： Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker , Mark Wayne VanderWiele
IPC分类号： G06F9/46
摘要： Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.
摘要翻译： 说明性实施例提供了一种计算机实现的方法，数据处理系统和用于锁定争用减少的计算机程序产品。 在一个示例性实施例中，计算机实现的方法向活动线程提供锁定，增加锁定计数器，接收去调度活动线程的请求，并且确定锁是否被活动线程保持。 计算机实现的方法响应于锁定被活动线程保持的确定，将第一预定量添加到活动线程的时间片。
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3.发明申请公开(公告)号：US20100229181A1
公开(公告)日：2010-09-09
申请号：US12398230
申请日：2009-03-05
申请人： Manish Ahuja , Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker
发明人： Manish Ahuja , Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker
CPC分类号： G06F9/4856 , G06F9/45558 , G06F2009/4557
摘要： Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.
摘要翻译： 在虚拟分区数据处理系统的虚拟分区之间安排分区迁移。 虚拟分区数据处理系统是一种无时间系统，其中周期性定时器中断不能保证以规定的时间间隔发送到处理器。 接收到分区迁移的请求。 确定定时中断之间的间隙。 然后，分区迁移计划发生在最大的差距内。
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公开(公告)号：US20080114971A1
公开(公告)日：2008-05-15
申请号：US11559426
申请日：2006-11-14
CPC分类号： G06F9/3863 , G06F9/3806
摘要： A computer implemented method, apparatus, and computer program product for preserving branch history data. The process creates a branch history table in a buffer. The process saves an address for each executed branch instruction that occurs during execution of code in the branch history table to form branch history data. In response to detecting an exception, the process saves the branch history data to an allocated memory space to form a branch history snapshot.
摘要翻译： 一种用于保存分支历史数据的计算机实现的方法，装置和计算机程序产品。 该进程在缓冲区中创建一个分支历史表。 该过程保存在分支历史表中的代码执行期间发生的每个执行的分支指令的地址以形成分支历史数据。 响应于检测到异常，该过程将分支历史数据保存到分配的存储器空间以形成分支历史快照。
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5.发明授权公开(公告)号：US08307367B2
公开(公告)日：2012-11-06
申请号：US12398230
申请日：2009-03-05
申请人： Manish Ahuja , Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker
发明人： Manish Ahuja , Nathan D. Fontenot , Jacob Lorien Moilanen , Joel Howard Schopp , Michael Thomas Strosaker
CPC分类号： G06F9/4856 , G06F9/45558 , G06F2009/4557
摘要： Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.
摘要翻译： 在虚拟分区数据处理系统的虚拟分区之间安排分区迁移。 虚拟分区数据处理系统是一种无时间系统，其中周期性定时器中断不能保证以规定的时间间隔发送到处理器。 接收到分区迁移的请求。 确定定时中断之间的间隙。 然后，分区迁移计划发生在最大的差距内。
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公开(公告)号：US20090282217A1
公开(公告)日：2009-11-12
申请号：US12116268
申请日：2008-05-07
IPC分类号： G06F9/22
CPC分类号： G06F9/5038 , G06F2209/501 , Y02D10/22
摘要： A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.
摘要翻译： 一种计算机实现的方法，数据处理系统和计算机程序产品，用于在对数据流进行操作的流水线中动态调度算法。 说明性实施例确定流水线中的多个算法中的每个算法的计算成本。 流水线中的多个算法以第一顺序算法顺序处理输入数据流。 说明性实施例在流水线中重新排序多个算法，以基于每个算法的计算成本形成第二顺序算法顺序。 然后可以以第二顺序算法顺序执行多个算法。 当说明性实施例将一个备用处理单元分配给流水线末尾的算法时，重新确定流水线中的多个算法中的每个算法的计算成本。
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7.发明申请REDUCED MEMORY TRAFFIC VIA DETECTION AND TRACKING OF TEMPORALLY SILENT STORES 有权通过检测和跟踪临时水泥仓储减少记忆交通公开(公告)号：US20080052469A1
公开(公告)日：2008-02-28
申请号：US11466794
申请日：2006-08-24
IPC分类号： G06F13/00
CPC分类号： G06F12/0891 , G06F12/0833
摘要： A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.
摘要翻译： 一种计算机实现的方法，数据处理系统和计算机程序产品，用于通过检测和跟踪暂时无声的商店来减少内存流量。 当检测到包括地址和数据值的存储器存储到高速缓存中时，确定高速缓存行中的高速缓存行包含与存储器存储器中的地址相同的地址。 然后，确定先前将用于高速缓存行的暂定高速缓存行无效信号发送到网络中的其他数据处理系统以暂时使高速缓存行无效。 如果存储器是时间无声的存储器，则将高速缓存行重新生效信号发送到其他数据处理系统以清除用于高速缓存行的暂定无效信号。
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公开(公告)号：US08365172B2
公开(公告)日：2013-01-29
申请号：US12116268
申请日：2008-05-07
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/501 , Y02D10/22
摘要： A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.
摘要翻译： 一种计算机实现的方法，数据处理系统和计算机程序产品，用于在对数据流进行操作的流水线中动态调度算法。 说明性实施例确定流水线中的多个算法中的每个算法的计算成本。 流水线中的多个算法以第一顺序算法顺序处理输入数据流。 说明性实施例在流水线中重新排序多个算法，以基于每个算法的计算成本形成第二顺序算法顺序。 然后可以以第二顺序算法顺序执行多个算法。 当说明性实施例将一个备用处理单元分配给流水线末尾的算法时，重新确定流水线中的多个算法中的每个算法的计算成本。
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9.发明授权Reduced memory traffic via detection and tracking of temporally silent stores 有权通过检测和跟踪暂时无声的商店来减少内存流量公开(公告)号：US07571286B2
公开(公告)日：2009-08-04
申请号：US11466794
申请日：2006-08-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0833
摘要： A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.
摘要翻译： 一种计算机实现的方法，数据处理系统和计算机程序产品，用于通过检测和跟踪暂时无声的商店来减少内存流量。 当检测到包括地址和数据值的存储器存储到高速缓存中时，确定高速缓存行中的高速缓存行包含与存储器存储器中的地址相同的地址。 然后，确定先前将用于高速缓存行的暂定高速缓存行无效信号发送到网络中的其他数据处理系统以暂时使高速缓存行无效。 如果存储器是时间无声的存储器，则将高速缓存行重新生效信号发送到其他数据处理系统以清除用于高速缓存行的暂定无效信号。
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公开(公告)号：US07958381B2
公开(公告)日：2011-06-07
申请号：US12147565
申请日：2008-06-27
IPC分类号： G06F1/00
CPC分类号： G06F3/0625 , G06F1/3221 , G06F3/0634 , G06F3/0683 , Y02D10/154
摘要： A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.
摘要翻译： 在说明性实施例中提供了用于在多路径数据通信中节能的方法，系统和计算机可用程序产品。 确定几个I / O设备中的每一个的当前利用率。 来自多个I / O设备的I / O设备是否可以在不违反规则的情况下断电而进行违规确定。 响应于违规判定为假，I / O设备关闭电源。 可以确定在多路径I / O配置中是否需要额外的I / O设备的加电确定。 I / O设备可能位于，上电并可用于多路径I / O配置。 可以在等待时间确定I / O设备的等待时间是否可以在需要额外的I / O设备之前经过。 上电可能不迟于需要额外的I / O设备之前的延迟时间。
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