公开(公告)号：US07893724B2

公开(公告)日：2011-02-22

申请号：US11985340

申请日：2007-11-13

Applicant: Nathan Moyal ,  Jonathon Stiff

Inventor： Nathan Moyal ,  Jonathon Stiff

IPC: G01R25/00

CPC classification number: H03K5/135 ,  H03K5/156

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract translation: 用于对准包括第一和第二信号的两个或多个信号的电路和方法。 在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出， 第一信号基本上与第二信号的偏移副本对准。 还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。 一些实施例可以包括省电模式。

公开(公告)号：US20080136470A1

公开(公告)日：2008-06-12

申请号：US11985340

申请日：2007-11-13

Applicant: Nathan Moyal ,  Jonathon Stiff

Inventor： Nathan Moyal ,  Jonathon Stiff

IPC: H03L7/00

CPC classification number: H03K5/135 ,  H03K5/156

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract translation: 用于对准包括第一和第二信号的两个或多个信号的电路和方法。 在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出， 第一信号基本上与第二信号的偏移副本对准。 还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。 一些实施例可以包括省电模式。

公开(公告)号：US07123065B1

公开(公告)日：2006-10-17

申请号：US10847930

申请日：2004-05-17

Applicant: Nathan Moyal

Inventor： Nathan Moyal

IPC: H03L7/06

CPC classification number: H03L7/107 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0995 ,  H03L2207/06

Abstract: The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired output frequency. If the actual output frequency is above the desired output frequency a signal is added to the forward path of the PLL to decrease the frequency of the PLL oscillator. If the actual output frequency is below the desired output frequency a signal is added to the forward path of the PLL to increase the frequency of the PLL oscillator.

Abstract translation: 本发明向锁相环（PLL）添加附加的反馈环路。 附加的反馈回路检测PLL的实际输出频率是否高于或低于所需的输出频率。 如果实际的输出频率高于所需的输出频率，则将一个信号添加到PLL的正向通道，以降低PLL振荡器的频率。 如果实际的输出频率低于期望的输出频率，则将一个信号添加到PLL的正向通道，以增加PLL振荡器的频率。

公开(公告)号：US07432749B1

公开(公告)日：2008-10-07

申请号：US10875667

申请日：2004-06-23

Applicant: Mark Gehring ,  Nathan Moyal

Inventor： Mark Gehring ,  Nathan Moyal

IPC: H03L7/06

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/18

Abstract: A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

Abstract translation: 一种用于提供诸如高频时钟信号的周期性时钟信号的电路和方法。 在一个示例中，电路可以包括具有压控振荡器的锁相环电路，压控振荡器具有电压输入，校准输入和时钟信号输出; 以及用于在锁相环操作期间动态地校准锁相环的工作频率的逻辑电路。 在一个实施例中，逻辑电路可以将参考电压中的压控振荡器的输入电压进行比较，如果输入电压低于参考电压，则逻辑电路降低锁相环电路的工作频率。 逻辑电路可以将压控振荡器的输入电压与参考电压进行比较，如果输入电压高于参考电压，则逻辑电路增加了锁相环电路的工作频率。

公开(公告)号：US08019299B1

公开(公告)日：2011-09-13

申请号：US11154097

申请日：2005-06-15

Applicant: Nathan Moyal ,  David G. Wright

Inventor： Nathan Moyal ,  David G. Wright

IPC: H04B1/18

CPC classification number: H03J1/0091 ,  H03J1/005

Abstract: One embodiment includes a system configured to identify a preferred channel for radio communication from a plurality of consecutive integer frequencies including preferred channels and non-preferred channels, the system further to generate a plurality of radio channels corresponding to a plurality of consecutive integer frequencies based on a generation of reference frequencies, identifies preferred channels and non-preferred channels from the plurality of radio channels, where frequency synthesizer settling times of the preferred channels are faster than frequency synthesizer settling times of the non-preferred channels, scan the preferred channels for radio activity, select one of preferred channels responsive to the scanned radio activity; and utilize one of the reference frequencies to generate a radio frequency corresponding to the selected one of the preferred channels.

Abstract translation: 一个实施例包括被配置为从包括优选信道和非优选信道的多个连续整数频率中识别用于无线电通信的优选信道的系统，所述系统还用于基于多个连续整数频率生成对应于多个连续整数频率的多个无线电信道 参考频率的一代识别来自多个无线电信道的优选信道和非优选信道，其中优选信道的频率合成器建立时间比非优选信道的频率合成器建立时间快，扫描优选信道用于无线电 活动，选择响应于扫描的无线电活动的首选频道之一; 并且利用参考频率之一来产生对应于所选择的一个优选频道的射频。

公开(公告)号：US20070082635A1

公开(公告)日：2007-04-12

申请号：US11467346

申请日：2006-08-25

Applicant: Mark Gehring ,  Nathan Moyal

Inventor： Mark Gehring ,  Nathan Moyal

IPC: H04B1/18 ,  H04B7/00 ,  H04B1/06

CPC classification number: H03L7/0802 ,  H03L7/0891 ,  H03L7/14 ,  H03L7/18

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract translation: 在具有间歇操作无线电的系统中，其频率由锁相环（PLL）控制，一种用于通过在PLL之后对PLL中的控制电容器进行三态化来降低PLL消耗的功率的方法和系统 稳定在设计频率。 电容器稳定后，PLL中某些组件的电源减少。

公开(公告)号：US06771096B1

公开(公告)日：2004-08-03

申请号：US10105687

申请日：2002-03-25

Applicant: Steve Meyers ,  Nathan Moyal

Inventor： Steve Meyers ,  Nathan Moyal

IPC: G01R2500

CPC classification number: H03L7/0891 ,  G01R25/005 ,  H03D13/004

Abstract: A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/−2&pgr;. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.

Abstract translation: 相位频率检测器（PFD）利用滞后死区避免，同时最大化线性范围并最小化PFD电路消耗的功率和面积。 PFD在复位逻辑门中包括滞后，这防止复位逻辑门在PFD的每个校正脉冲到达最终稳态直流电压值之前切换其输出。 PFD响应模拟理想的响应，使得线性度保持在相位锁定点处，并且在+/- 2pi的整个线性范围内。 此外，滞后复位逻辑门监视校正脉冲，以将适当量的时间延迟插入到PFD复位通道中，而不引入额外的延迟元件。 结果，由于从设计中消除了额外的延迟元件的事实，PHD的线性范围被最大化，并且PFD消耗的功率和面积被最小化。

公开(公告)号：US09104273B1

公开(公告)日：2015-08-11

申请号：US12395969

申请日：2009-03-02

Applicant: Dana Olson ,  Nathan Moyal

Inventor： Dana Olson ,  Nathan Moyal

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G06F2203/04104

Abstract: A capacitance measurement sensor, having a voltage subtractor that rejects common signals between the columns or rows of a touch sensor matrix depending on which are driven and which are being sensed, is described.

Abstract translation: 描述了具有电压减法器的电容测量传感器，该电压减除器拒绝根据驱动和被感测的触摸传感器矩阵的列或行之间的公共信号。

公开(公告)号：US08321174B1

公开(公告)日：2012-11-27

申请号：US12239692

申请日：2008-09-26

Applicant: Nathan Moyal ,  Dana Olson

Inventor： Nathan Moyal ,  Dana Olson

IPC: G01C9/00

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: A system and method for measuring capacitance of a capacitive sensor array is disclosed. Upon measuring the capacitance, position information with respect to the sensor array may be determined. A column, a first row, and a second row of a capacitive sensor array may be selected. The first row and the second row intersect with the column of the capacitive sensor array. A differential capacitance between the first row and the second row may be measured. The differential capacitance may be utilized in determining a location of an object proximate to the capacitive sensor array.

Abstract translation: 公开了一种用于测量电容式传感器阵列的电容的系统和方法。 在测量电容时，可以确定相对于传感器阵列的位置信息。 可以选择电容式传感器阵列的列，第一行和第二行。 第一行和第二行与电容式传感器阵列的列相交。 可以测量第一行和第二行之间的差分电容。 差分电容可用于确定靠近电容传感器阵列的物体的位置。

公开(公告)号：US08112054B2

公开(公告)日：2012-02-07

申请号：US11467346

申请日：2006-08-25

Applicant: Mark R. Gehring ,  Nathan Moyal

Inventor： Mark R. Gehring ,  Nathan Moyal

IPC: H04B1/06

CPC classification number: H03L7/0802 ,  H03L7/0891 ,  H03L7/14 ,  H03L7/18

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract translation: 在具有间歇操作无线电的系统中，其频率由锁相环（PLL）控制，一种用于通过在PLL之后对PLL中的控制电容器进行三态化来降低PLL消耗的功率的方法和系统 稳定在设计频率。 电容器稳定后，PLL中某些组件的电源减少。