公开(公告)号：US09703740B2

公开(公告)日：2017-07-11

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

公开(公告)号：US09652370B2

公开(公告)日：2017-05-16

申请号：US14097924

申请日：2013-12-05

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones

IPC: G06F13/36 ,  G06F12/00 ,  H04L12/947 ,  H04L12/931 ,  G06F13/40 ,  G06F13/38 ,  H04L12/751

CPC classification number: G06F12/00 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  H04L45/02 ,  H04L49/25 ,  H04L49/35

Abstract: Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.

公开(公告)号：US10176137B2

公开(公告)日：2019-01-08

申请号：US14997912

申请日：2016-01-18

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/36 ,  G06F9/50

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

公开(公告)号：US20160132453A1

公开(公告)日：2016-05-12

申请号：US14997912

申请日：2016-01-18

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4045 ,  G06F9/5077 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract translation: 选择性透明的桥接器有助于将PCI设备作为PCI至PCI桥接器呈现给主机，但是选择性地将硬件与主机总线隔离并隔离。 PCI配置可以通过标准的PCI Express配置机制来实现，但不是直接配置设备，而是选择性透明的桥接器中的配置处理器可能会拦截来自主机的配置数据包，并创建一个虚拟配置，以改变总线拓扑的显示方式 主人。 设备由配置处理器选择性地隐藏和管理，导致简化的复杂性和总线深度。 由于选择性透明的桥接器作为透明桥显示给主机，因此不需要特殊的驱动程序或资源预分配，尽管选择性透明的桥完全支持特殊驱动程序和/或资源预分配。 因此，位于/连接在桥下游的设备因此可以与未修改的驱动器一起工作。

公开(公告)号：US20140372657A1

公开(公告)日：2014-12-18

申请号：US13918308

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Jonathan W. Hearn ,  Jason D. Tongen

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Abstract translation: 可以在PCIe子系统的虚拟拓扑和物理拓扑之间建立映射和对应关系，并且主机可以呈现虚拟拓扑而不是实际物理拓扑。 半透明桥可以将上游主机耦合到PCIe子系统，该PCIe子系统包括中间桥接器以及从中间桥接器下游耦合的各自的PCIe端点。 中介桥可以从主机隐藏，而相应的PCIe端点可能对于主机是可见的。 配置块可以在设置模式期间向上游主机提供对应于中间交换机的第一存储器分配信息，响应于上游主机期望与各个PCIe端点对应的第二存储器分配信息。 然后，配置块可以在运行时模式期间向上游主机提供响应于预期第二存储器分配信息的上游主机的第二存储器分配信息。

公开(公告)号：US20160188518A1

公开(公告)日：2016-06-30

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US09286258B2

公开(公告)日：2016-03-15

申请号：US13918611

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US20150161068A1

公开(公告)日：2015-06-11

申请号：US14097924

申请日：2013-12-05

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones

IPC: G06F13/40

CPC classification number: G06F12/00 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  H04L45/02 ,  H04L49/25 ,  H04L49/35

Abstract: Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.

Abstract translation: 智能桥梁使用。 智能桥包括功能单元，存储器和用于使用路由表在主机和多个设备之间路由数据的交换机。 桥接器将转发地址范围（FAR）存储为设备所需的硬件存储器资源的桥接表示。 FAR是第一个规定的最小尺寸的整数倍，并与第一个规定的最小尺寸对齐。 基于FAR的起始地址，桥接表示被转换为包括多个虚拟存储器资源的端点表示。 每个虚拟存储器资源具有相应的子地址范围，其尺寸是第二规定的最小尺寸的2倍的幂，小于第一规定的最小尺寸，并且相应地对齐。 端点表示可由交换机或主机将虚拟内存资源分配给设备。

公开(公告)号：US20140372660A1

公开(公告)日：2014-12-18

申请号：US13918435

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: A PCIe subsystem may be coupled to a host by a system extender adapted to perform PCIe packet routing based on packet type. A first TLP (transport layer packet) type router may receive PCIe packets, and selectively route the PCIe packets according to the type of the packet through a corresponding path of at least two alternate paths. A second TLP type router may receive the routed packet through a first path if the PCIe packet was routed through the first path, and may receive the routed packet through a second path if the routed packet was routed through the second path. A non transparent bridge may be coupled between the first TLP type router block and the second TLP type router block along the second path, while the first path may be a pass-through path from the first TLP type router block to the second TLP type router block.

Abstract translation: PCIe子系统可以由适于基于分组类型执行PCIe分组路由的系统扩展器耦合到主机。 第一TLP（传输层分组）型路由器可以接收PCIe分组，并且根据分组的类型通过至少两个备选路径的对应路径选择性地路由PCIe分组。 如果PCIe分组通过第一路径路由，则第二TLP类型路由器可以经由第一路径接收路由分组，并且如果路由分组被路由通过第二路径，则可以通过第二路径接收路由分组。 第一TLP型路由器块和第二TLP型路由器块之间可以沿着第二路径耦合非透明桥，而第一路径可以是从第一TLP型路由器块到第二TLP型路由器的直通路径 块。

公开(公告)号：US20140372641A1

公开(公告)日：2014-12-18

申请号：US13918685

申请日：2013-06-14

Applicant: National Instruments Corporation

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40

CPC classification number: G06F13/4045 ,  G06F9/5077 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract translation: 选择性透明的桥接器有助于将PCI设备作为PCI至PCI桥接器呈现给主机，但是选择性地将硬件与主机总线隔离并隔离。 PCI配置可以通过标准的PCI Express配置机制来实现，但不是直接配置设备，而是选择性透明的桥接器中的配置处理器可以拦截来自主机的配置数据包，并创建一个虚拟配置，以改变总线拓扑的显示方式 主人。 设备由配置处理器选择性地隐藏和管理，导致简化的复杂性和总线深度。 由于选择性透明的桥接器作为透明桥显示给主机，因此不需要特殊的驱动程序或资源预分配，尽管选择性透明的桥完全支持特殊驱动程序和/或资源预分配。 因此，位于/连接在桥下游的设备因此可以与未修改的驱动器一起工作。