公开(公告)号：US09703740B2

公开(公告)日：2017-07-11

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

公开(公告)号：US09965371B2

公开(公告)日：2018-05-08

申请号：US14861006

申请日：2015-09-22

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Feng Jiang ,  Ryan C. Croom ,  Jason D. Tongen

IPC: G06F11/30 ,  G06F11/32

CPC classification number: G06F11/3051 ,  G06F11/00 ,  G06F11/3027 ,  G06F11/328

Abstract: System and method for determining and conveying connectivity of cabled computer peripherals to a user. Characteristic information regarding each of multiple devices connected to a computer system in a system hierarchy of a bus networked system may be stored, including a device hierarchy associated with each device that identifies respective hardware nodes included in the device, and one or more visual attributes of the device. Respective system positions may be automatically determined for at least some of the devices based on the device hierarchy. A respective point of reference of at least one device may be determined based on the characteristic information of one or more of the devices. The computer system may generate information that indicates the respective system position of the at least one device relative to the respective point of reference of the device, which is useable to visually identify the device in the bus networked system.

公开(公告)号：US09311266B2

公开(公告)日：2016-04-12

申请号：US13918308

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Jonathan W. Hearn ,  Jason D. Tongen

IPC: G06F15/177 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Abstract translation: 可以在PCIe子系统的虚拟拓扑和物理拓扑之间建立映射和对应关系，并且主机可以呈现虚拟拓扑而不是实际物理拓扑。 半透明桥可以将上游主机耦合到PCIe子系统，该PCIe子系统包括中间桥接器以及从中间桥接器下游耦合的各自的PCIe端点。 中介桥可以从主机隐藏，而相应的PCIe端点可能对于主机是可见的。 配置块可以在设置模式期间向上游主机提供对应于中间交换机的第一存储器分配信息，响应于上游主机期望与各个PCIe端点对应的第二存储器分配信息。 然后，配置块可以在运行时模式期间向上游主机提供响应于预期第二存储器分配信息的上游主机的第二存储器分配信息。

公开(公告)号：US20140372741A1

公开(公告)日：2014-12-18

申请号：US13918611

申请日：2013-06-14

Applicant: National Instruments Corporation

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F13/40 ,  G06F9/44

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US20170031796A1

公开(公告)日：2017-02-02

申请号：US14861006

申请日：2015-09-22

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Feng Jiang ,  Ryan C. Croom ,  Jason D. Tongen

IPC: G06F11/30 ,  G06F11/32

CPC classification number: G06F11/3051 ,  G06F11/00 ,  G06F11/3027 ,  G06F11/328

Abstract: System and method for determining and conveying connectivity of cabled computer peripherals to a user. Characteristic information regarding each of multiple devices connected to a computer system in a system hierarchy of a bus networked system may be stored, including a device hierarchy associated with each device that identifies respective hardware nodes included in the device, and one or more visual attributes of the device. Respective system positions may be automatically determined for at least some of the devices based on the device hierarchy. A respective point of reference of at least one device may be determined based on the characteristic information of one or more of the devices. The computer system may generate information that indicates the respective system position of the at least one device relative to the respective point of reference of the device, which is useable to visually identify the device in the bus networked system.

Abstract translation: 用于确定和传送电缆计算机外围设备到用户的连接性的系统和方法。 可以存储关于在总线网络系统的系统层级中连接到计算机系统的多个设备中的每一个的特性信息，包括与标识设备中包括的各个硬件节点的每个设备相关联的设备层级，以及一个或多个视觉属性 装置。 可以基于设备层次结构为至少一些设备自动确定各个系统位置。 可以基于一个或多个设备的特征信息来确定至少一个设备的相应参考点。 计算机系统可以生成指示相对于设备的相应参考点的至少一个设备的相应系统位置的信息，其可用于视觉识别总线网络系统中的设备。

公开(公告)号：US20140372657A1

公开(公告)日：2014-12-18

申请号：US13918308

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Jonathan W. Hearn ,  Jason D. Tongen

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Abstract translation: 可以在PCIe子系统的虚拟拓扑和物理拓扑之间建立映射和对应关系，并且主机可以呈现虚拟拓扑而不是实际物理拓扑。 半透明桥可以将上游主机耦合到PCIe子系统，该PCIe子系统包括中间桥接器以及从中间桥接器下游耦合的各自的PCIe端点。 中介桥可以从主机隐藏，而相应的PCIe端点可能对于主机是可见的。 配置块可以在设置模式期间向上游主机提供对应于中间交换机的第一存储器分配信息，响应于上游主机期望与各个PCIe端点对应的第二存储器分配信息。 然后，配置块可以在运行时模式期间向上游主机提供响应于预期第二存储器分配信息的上游主机的第二存储器分配信息。

公开(公告)号：US20160188518A1

公开(公告)日：2016-06-30

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US09286258B2

公开(公告)日：2016-03-15

申请号：US13918611

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US08938559B2

公开(公告)日：2015-01-20

申请号：US13645864

申请日：2012-10-05

Applicant: National Instruments Corporation

Inventor： Sundeep Chandhoke ,  Jason D. Tongen

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F13/404 ,  G06F2213/0026

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract translation: 分布式系统中不同内存映射域之间同步数据传输的技术。 一种方法包括配置具有等时周期的等时引擎。 该方法还包括在同步周期的周期的指定部分期间，通过存储器映射的结构从第一存储器传送数据到第二存储器。 第一存储器包括在存储器映射结构的第一存储器映射域中的第一设备中，并且第二存储器包括在存储器映射结构的第二存储器映射域中的第二设备中。 该方法还可以包括翻译与传送相关的一个或多个地址。 存储器映射结构可以是PCI-Express结构。 传输可以由DMA控制器执行。 不透明的桥可以分离第一和第二存储器映射域并且可以执行转换。

公开(公告)号：US20140101347A1

公开(公告)日：2014-04-10

申请号：US13645864

申请日：2012-10-05

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Sundeep Chandhoke ,  Jason D. Tongen

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F13/404 ,  G06F2213/0026

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract translation: 分布式系统中不同内存映射域之间同步数据传输的技术。 一种方法包括配置具有等时周期的等时引擎。 该方法还包括在同步周期的周期的指定部分期间，通过存储器映射的结构从第一存储器传送数据到第二存储器。 第一存储器包括在存储器映射结构的第一存储器映射域中的第一设备中，并且第二存储器包括在存储器映射结构的第二存储器映射域中的第二设备中。 该方法还可以包括翻译与传送相关的一个或多个地址。 存储器映射结构可以是PCI-Express结构。 传输可以由DMA控制器执行。 不透明的桥可以分离第一和第二存储器映射域并且可以执行转换。