公开(公告)号：US09703740B2

公开(公告)日：2017-07-11

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

公开(公告)号：US09965371B2

公开(公告)日：2018-05-08

申请号：US14861006

申请日：2015-09-22

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Feng Jiang ,  Ryan C. Croom ,  Jason D. Tongen

IPC: G06F11/30 ,  G06F11/32

CPC classification number: G06F11/3051 ,  G06F11/00 ,  G06F11/3027 ,  G06F11/328

Abstract: System and method for determining and conveying connectivity of cabled computer peripherals to a user. Characteristic information regarding each of multiple devices connected to a computer system in a system hierarchy of a bus networked system may be stored, including a device hierarchy associated with each device that identifies respective hardware nodes included in the device, and one or more visual attributes of the device. Respective system positions may be automatically determined for at least some of the devices based on the device hierarchy. A respective point of reference of at least one device may be determined based on the characteristic information of one or more of the devices. The computer system may generate information that indicates the respective system position of the at least one device relative to the respective point of reference of the device, which is useable to visually identify the device in the bus networked system.

公开(公告)号：US20210248100A1

公开(公告)日：2021-08-12

申请号：US17241394

申请日：2021-04-27

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric L. Singer ,  Jason W. Frels ,  Jonathan W. Hearn

IPC: G06F13/40

Abstract: Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

公开(公告)号：US20160188518A1

公开(公告)日：2016-06-30

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US09286258B2

公开(公告)日：2016-03-15

申请号：US13918611

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F9/24 ,  G06F15/177 ,  G06F13/40 ,  G06F9/44 ,  G06F12/02 ,  G06F13/38 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US20140372641A1

公开(公告)日：2014-12-18

申请号：US13918685

申请日：2013-06-14

Applicant: National Instruments Corporation

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40

CPC classification number: G06F13/4045 ,  G06F9/5077 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract translation: 选择性透明的桥接器有助于将PCI设备作为PCI至PCI桥接器呈现给主机，但是选择性地将硬件与主机总线隔离并隔离。 PCI配置可以通过标准的PCI Express配置机制来实现，但不是直接配置设备，而是选择性透明的桥接器中的配置处理器可以拦截来自主机的配置数据包，并创建一个虚拟配置，以改变总线拓扑的显示方式 主人。 设备由配置处理器选择性地隐藏和管理，导致简化的复杂性和总线深度。 由于选择性透明的桥接器作为透明桥显示给主机，因此不需要特殊的驱动程序或资源预分配，尽管选择性透明的桥完全支持特殊驱动程序和/或资源预分配。 因此，位于/连接在桥下游的设备因此可以与未修改的驱动器一起工作。

公开(公告)号：US11023402B2

公开(公告)日：2021-06-01

申请号：US16751934

申请日：2020-01-24

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric L. Singer ,  Jason W. Frels ,  Jonathan W. Hearn

IPC: G06F13/40

Abstract: Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

公开(公告)号：US20210004342A1

公开(公告)日：2021-01-07

申请号：US16751934

申请日：2020-01-24

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric L. Singer ,  Jason W. Frels ,  Jonathan W. Hearn

IPC: G06F13/40

Abstract: Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

公开(公告)号：US09311266B2

公开(公告)日：2016-04-12

申请号：US13918308

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Jonathan W. Hearn ,  Jason D. Tongen

IPC: G06F15/177 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Abstract translation: 可以在PCIe子系统的虚拟拓扑和物理拓扑之间建立映射和对应关系，并且主机可以呈现虚拟拓扑而不是实际物理拓扑。 半透明桥可以将上游主机耦合到PCIe子系统，该PCIe子系统包括中间桥接器以及从中间桥接器下游耦合的各自的PCIe端点。 中介桥可以从主机隐藏，而相应的PCIe端点可能对于主机是可见的。 配置块可以在设置模式期间向上游主机提供对应于中间交换机的第一存储器分配信息，响应于上游主机期望与各个PCIe端点对应的第二存储器分配信息。 然后，配置块可以在运行时模式期间向上游主机提供响应于预期第二存储器分配信息的上游主机的第二存储器分配信息。

公开(公告)号：US09244874B2

公开(公告)日：2016-01-26

申请号：US13918685

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40 ,  G06F9/50

CPC classification number: G06F13/4045 ,  G06F9/5077 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract translation: 选择性透明的桥接器有助于将PCI设备作为PCI至PCI桥接器呈现给主机，但是选择性地将硬件与主机总线隔离并隔离。 PCI配置可以通过标准的PCI Express配置机制来实现，但不是直接配置设备，而是选择性透明的桥接器中的配置处理器可能会拦截来自主机的配置数据包，并创建一个虚拟配置，以改变总线拓扑的显示方式 主人。 设备由配置处理器选择性地隐藏和管理，导致简化的复杂性和总线深度。 由于选择性透明的桥接器作为透明桥显示给主机，因此不需要特殊的驱动程序或资源预分配，尽管选择性透明的桥完全支持特殊驱动程序和/或资源预分配。 因此，位于/连接在桥下游的设备因此可以与未修改的驱动器一起工作。