-
1.发明授权Circuit and method using distributed phase change elements for across-chip temperature profiling 有权使用分布式相变元件进行跨芯片温度分析的电路和方法公开(公告)号：US07882455B2
公开(公告)日：2011-02-01
申请号：US12117784
申请日：2008-05-09
IPC分类号： G06F17/50
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译： 公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。 这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。 这些相变元件被编程为具有基本上相同的无定形电阻。 每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便 描述半导体芯片上的温度梯度。 一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。
-
2.发明申请Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling 有权用于跨芯片温度分布的分布相变元件的电路和方法公开(公告)号：US20090282375A1
公开(公告)日：2009-11-12
申请号：US12117784
申请日：2008-05-09
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译： 公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。 这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。 这些相变元件被编程为具有基本上相同的无定形电阻。 每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便 描述半导体芯片上的温度梯度。 一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。
-
3.发明申请RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS 有权可靠性评估和系统故障警告使用芯片参数监视器的方法公开(公告)号：US20120105240A1
公开(公告)日：2012-05-03
申请号：US13344178
申请日：2012-01-05
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。
-
4.发明授权HDL design structure for integrating test structures into an integrated circuit design 有权用于将测试结构集成到集成电路设计中的HDL设计结构公开(公告)号：US07884599B2
公开(公告)日：2011-02-08
申请号：US12106361
申请日：2008-04-21
申请人： Nazmul Habib , Robert McMahon , Troy Perry
发明人： Nazmul Habib , Robert McMahon , Troy Perry
IPC分类号： G01R31/28
CPC分类号： G01R31/31723 , G01R31/31724 , G01R31/318511
摘要： A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.
摘要翻译： 一种硬件描述语言（HDL）设计结构，用于在集成电路上执行特定于设备的测试和获取参数数据，使得每个芯片可以单独测试，而不需要过多的测试时间要求，附加的硅或特殊测试设备。 HDL设计结构包括集成到IC设计中的至少一个设备测试结构的功能表示，该设计测试与IC中包含的所选设备集相同或几乎相同的一组虚拟设备。 测试结构根据客户要求和设计要求从被测器件（DUT）库集成。 所选测试结构的功能表示进一步优先排列，并按优先级顺序分配给设计中的设计元素。 放置算法使用设计，布局和制造要求将测试结构的选定功能表示放置在设计的最终布局中。
-
5.发明申请公开(公告)号：US20090210201A1
公开(公告)日：2009-08-20
申请号：US12031079
申请日：2008-02-14
CPC分类号： G06F17/505 , G01R31/3008 , G06F17/5068 , H01L22/34
摘要： A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.
摘要翻译： 一种用于预测和控制泄漏的方法，其中将IDDQ预测宏放置在多个设计拓扑中，并且使用IDDQ预测宏来收集数据。 IDDQ预测宏被配置为使用IDDQ预测宏来测量半导体测试位置和划线中的至少一种设备类型的亚阈值泄漏和栅极泄漏并建立泄漏模型。 该方法将半导体测试现场测量和划线测量相关联，以建立划线控制限制，预测产品泄漏; 并使用泄漏模型为每个产品设置亚阈值泄漏限值和门泄漏限值。
-
6.发明申请HDL Design Structure for Integrating Test Structures into an Integrated Circuit Design 有权将测试结构集成到集成电路设计中的HDL设计结构公开(公告)号：US20080189671A1
公开(公告)日：2008-08-07
申请号：US12106361
申请日：2008-04-21
申请人： Nazmul Habib , Robert McMahon , Troy Perry
发明人： Nazmul Habib , Robert McMahon , Troy Perry
IPC分类号： G06F17/50
CPC分类号： G01R31/31723 , G01R31/31724 , G01R31/318511
摘要： A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.
摘要翻译： 一种硬件描述语言（HDL）设计结构，用于在集成电路上执行特定于设备的测试和获取参数数据，使得每个芯片可以单独测试，而不需要过多的测试时间要求，附加的硅或特殊测试设备。 HDL设计结构包括集成到IC设计中的至少一个设备测试结构的功能表示，该设计测试与IC中包含的所选设备集相同或几乎相同的一组虚拟设备。 测试结构根据客户要求和设计要求从被测器件（DUT）库集成。 所选测试结构的功能表示进一步优先排列，并按优先级顺序分配给设计中的设计元素。 放置算法使用设计，布局和制造要求将测试结构的选定功能表示放置在设计的最终布局中。
-
7.发明授权Reliability evaluation and system fail warning methods using on chip parametric monitors 有权使用片上参数监视器的可靠性评估和系统故障预警方法公开(公告)号：US08095907B2
公开(公告)日：2012-01-10
申请号：US11874950
申请日：2007-10-19
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。
-
8.发明申请RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS 有权可靠性评估和系统故障警告使用芯片参数监视器的方法公开(公告)号：US20090106712A1
公开(公告)日：2009-04-23
申请号：US11874950
申请日：2007-10-19
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。
-
9.发明申请METHOD FOR GENERATING DEVICE MODEL OVERRIDES THROUGH THE USE OF ON-CHIP PARAMETRIC MEASUREMENT MACROS 审中-公开通过使用片上参数测量宏生成器件模型的方法公开(公告)号：US20090070722A1
公开(公告)日：2009-03-12
申请号：US11851073
申请日：2007-09-06
申请人： Jeanne Bickford , John R. Gross , Nazmul Habib , Robert McMahon
发明人： Jeanne Bickford , John R. Gross , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method generates area dependent design rules during semiconductor technology qualification by identifying the layout parametric variation in a semiconductor technology and establishing layout dependent design rules. This method applies the area dependent design rules to identify design sensitivity to area dependent design rules and to optimize semiconductor libraries and/or semiconductor products using an on-chip parametric monitor by designing processes for library elements, semiconductor design systems, and/or custom semiconductor products using the layout dependent design rules.
摘要翻译： 一种方法通过识别半导体技术中的布局参数变化和建立依赖于布局的设计规则，在半导体技术鉴定期间产生区域相关设计规则。 该方法应用区域依赖设计规则来识别对区域相关设计规则的设计灵敏度，并通过设计库单元，半导体设计系统和/或定制半导体的过程，使用片上参数监视器优化半导体库和/或半导体产品 产品采用布局依赖设计规则。
-
公开(公告)号：US20100254425A1
公开(公告)日：2010-10-07
申请号：US12819721
申请日：2010-06-21
申请人： Nazmul Habib , Chung Hon Lam , Robert McMahon
发明人： Nazmul Habib , Chung Hon Lam , Robert McMahon
IPC分类号： G01N25/02
CPC分类号： G01K11/06 , G01K7/16 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.
摘要翻译： 位于半导体芯片中的相变材料块被重置为非晶态。 相变材料块可以连接到可以以模拟输出格式或数字输出格式将测量的电阻数据传输到输入/输出焊盘的内部电阻测量电路。 根据环境温度，相变材料块的电阻变化。 通过测量与校准温度下的相变材料的电阻相比的分数电阻变化，可以精确地测量相变材料周围的区域的温度。 可以在内部电阻测量电路和输入/输出焊盘之间采用逻辑解码器和输入/输出电路。 可以在半导体芯片中采用包含相变材料块的多个温度检测电路，以便在芯片操作期间能够进行精确的温度分布。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.024 秒)
