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15 条记录 (耗时 0.048 秒)

    Decoupling arrangement
    6.
    发明授权
    Decoupling arrangement 有权
    去耦排列

    公开(公告)号：US08913364B2

    公开(公告)日：2014-12-16

    申请号：US13331500

    申请日：2011-12-20

    申请人： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

    发明人： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

    IPC分类号： H02H3/22

    CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

    摘要： In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

    摘要翻译： 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。

    Successive approximation analog-to-digital conversion architectural arrangement for receivers
    8.
    发明授权
    Successive approximation analog-to-digital conversion architectural arrangement for receivers 有权
    用于接收机的连续近似模数转换架构布置

    公开(公告)号：US08736480B1

    公开(公告)日：2014-05-27

    申请号：US13739510

    申请日：2013-01-11

    申请人： Nicholas P. Cowley ,  Isaac Ali ,  Viatcheslav I. Suetinov ,  Keith Pinson

    发明人： Nicholas P. Cowley ,  Isaac Ali ,  Viatcheslav I. Suetinov ,  Keith Pinson

    IPC分类号： H03M1/12

    CPC分类号： H03M1/0626 ,  H03M1/466

    摘要： An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.

    摘要翻译： 一种用于接收机的逐次逼近模数转换的装置和方法，包括在采样模式期间，将电容器阵列连接到耦合到多个放大输入信号的多个采样开关，并且在转换模式期间，连接到 将电容器阵列与比较器共用，并将电容器阵列与多个采样开关隔离。 另外，通过相位偏移处的样本的求和来进行滤波。

    Successive approximation analog-to-digital conversion with gain control for tuners
    9.
    发明授权
    Successive approximation analog-to-digital conversion with gain control for tuners 有权
    用于调谐器的增益控制的逐次近似模数转换

    公开(公告)号：US08730074B1

    公开(公告)日：2014-05-20

    申请号：US13740472

    申请日：2013-01-14

    申请人： Nicholas P. Cowley ,  Isaac Ali ,  Viatcheslav I. Suetinov ,  Keith Pinson

    发明人： Nicholas P. Cowley ,  Isaac Ali ,  Viatcheslav I. Suetinov ,  Keith Pinson

    IPC分类号： H03M1/00

    CPC分类号： H03M1/183

    摘要： A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.

    摘要翻译： 一种用于实现具有精细分辨率和最小额外电路的增益控制的方法和系统。 精细的数字增益控制可以结合在采样接收器的前端处的粗略的开关增益来部署。 精细数字增益控制机构被配置为接收输入信号并且适中的增益被施加到所接收的输入信号。 低噪声放大器（LNA）的输出连接到提供精细增益阶梯增益控制的开关衰减器。 该级的输出连接到开关级，其输出端连接到配置为将模拟波形转换为数字表示的电荷再分配逐次逼近寄存器数模转换器（SAR ADC）。

    Methods and arrangements for high-speed analog-to-digital conversion
    10.
    发明授权
    Methods and arrangements for high-speed analog-to-digital conversion 有权
    高速模数转换的方法和布置

    公开(公告)号：US08754800B2

    公开(公告)日：2014-06-17

    申请号：US13631949

    申请日：2012-09-29

    申请人： Nicholas P. Cowley ,  Isaac Ali ,  Keith Pinson ,  Viatcheslav I. Suetinov

    发明人： Nicholas P. Cowley ,  Isaac Ali ,  Keith Pinson ,  Viatcheslav I. Suetinov

    IPC分类号： H03M1/12

    CPC分类号： H03M1/12 ,  H03M1/183 ,  H03M1/38 ,  H03M1/70 ,  H04N5/243

    摘要： Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes.

    摘要翻译： 诸如用于信号的高速模数转换的硬件和/或代码的逻辑。 逻辑可以接收模拟信号作为采样接收机的输入。 采样接收器可以实现逐次逼近寄存器（SAR），模拟 - 数字转换器（ADC）以产生数字输出。 逻辑可以在采样模式下重新选择SAR ADC的比较器，以产生数字比较器输出，该数字比较器输出表示DAC电容上的电荷电压与阈值参考电压的比较。 数字比较器输出可以应用于自动增益控制（AGC）逻辑的输入。 AGC逻辑可以接收数字比较器信号，该数字比较器信号代表多个样本，采样周期的一个样本，允许AGC逻辑产生响应于总复合平均值和峰值幅度的增益控制信号。