公开(公告)号：US20080079139A1

公开(公告)日：2008-04-03

申请号：US11541124

申请日：2006-09-29

Applicant: Chunfei Ye ,  Boping Wu

Inventor： Chunfei Ye ,  Boping Wu

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于高性能集成电路的微通孔结构设计。 在这方面，引入集成电路芯片封装，其具有电介质层，电介质层中的电镀通孔和与电镀通孔耦合的微通孔，其中微通孔围绕轴线形成路径。 还公开并要求保护其他实施例。

公开(公告)号：US07649265B2

公开(公告)日：2010-01-19

申请号：US11541124

申请日：2006-09-29

Applicant: Chunfei Ye ,  Boping Wu

Inventor： Chunfei Ye ,  Boping Wu

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于高性能集成电路的微通孔结构设计。 在这方面，引入集成电路芯片封装，其具有电介质层，电介质层中的电镀通孔和与电镀通孔耦合的微通孔，其中微通孔围绕轴线形成路径。 还公开并要求保护其他实施例。

公开(公告)号：US20150131190A1

公开(公告)日：2015-05-14

申请号：US14534979

申请日：2014-11-06

Applicant: William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H9/04 ,  H05K1/02

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。

公开(公告)号：US08913364B2

公开(公告)日：2014-12-16

申请号：US13331500

申请日：2011-12-20

Applicant: William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H3/22

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。

公开(公告)号：US20130157482A1

公开(公告)日：2013-06-20

申请号：US13331500

申请日：2011-12-20

Applicant: William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H01R4/58

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.