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公开(公告)号：US20230388251A1
公开(公告)日：2023-11-30
申请号：US18199241
申请日：2023-05-18
IPC分类号： H04L49/552 , H04L49/9057 , H04L49/25 , H04L45/44 , H04L47/24 , H04L47/34 , H04L47/10 , H04L47/30 , H04L12/54
CPC分类号： H04L49/552 , H04L49/9057 , H04L49/25 , H04L45/44 , H04L47/24 , H04L47/34 , H04L47/39 , H04L47/30 , H04L12/56 , H04L2212/00 , H04L2012/5652
摘要： Tightly-coupled, loosely connected distributed systems can be implemented more energy efficient and optimized for computational overhead via multi-protocol heterogeneous packet-based transport. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets can be handled via Direct Memory Access. A write-only communication scheme can be implemented using doorbell and command registers for more efficient data reading and writing in distributed systems.
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公开(公告)号：US10708199B2
公开(公告)日：2020-07-07
申请号：US16055864
申请日：2018-08-06
IPC分类号： H04J3/22 , H04L12/939 , H04L12/861 , H04L12/947 , H04L12/721 , H04L12/851 , H04L12/54 , H04L12/801 , H04L12/835 , H04L12/70
摘要： Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.
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公开(公告)号：US20190058675A1
公开(公告)日：2019-02-21
申请号：US16055864
申请日：2018-08-06
IPC分类号： H04L12/939 , H04L12/861 , H04L12/947 , H04L12/721 , H04L12/801 , H04L12/851 , H04L12/54
摘要： Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.
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公开(公告)号：US07506286B2
公开(公告)日：2009-03-17
申请号：US11417355
申请日：2006-05-02
IPC分类号： G06F17/50
CPC分类号： G01R31/31705 , G01R31/318357 , G01R31/318364 , G06F17/5022
摘要： Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译： 公开了用于调试具有其中包括的仪表电路的电子系统的技术和系统。 这些技术和系统便于硬件描述语言（HDL）级别的硬件设计分析，诊断和调试。 虽然硬件设计（以HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但本发明可以使集成电路产品中的硬件设计在HDL级别进行全面分析，诊断和调试 速度。 以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。
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公开(公告)号：US07069526B2
公开(公告)日：2006-06-27
申请号：US11027052
申请日：2004-12-29
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318364 , G06F11/26 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
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公开(公告)号：US07356786B2
公开(公告)日：2008-04-08
申请号：US10915516
申请日：2004-08-09
IPC分类号： G06F17/50
CPC分类号： G01R31/31705 , G01R31/318357 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译： 描述了硬件描述语言（HDL）级别的分析，诊断和调试制造硬件设计的技术和系统。 虽然硬件设计（HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但是这些技术和系统使集成电路产品中的硬件设计能够在HDL中进行全面分析，诊断和调试 水平速度。 以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。
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公开(公告)号：US06581191B1
公开(公告)日：2003-06-17
申请号：US09724702
申请日：2000-11-28
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318364 , G06F11/26 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
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公开(公告)号：US07240303B1
公开(公告)日：2007-07-03
申请号：US10456768
申请日：2003-06-06
CPC分类号： G06F17/5022 , G01R31/31705 , G01R31/318364 , G06F11/3644
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译： 描述了硬件描述语言（HDL）级别的分析，诊断和调试制造硬件设计的技术和系统。 虽然硬件设计（HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但是这些技术和系统使集成电路产品中的硬件设计能够在HDL中进行全面分析，诊断和调试 水平速度。 以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。
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公开(公告)号：US07222315B2
公开(公告)日：2007-05-22
申请号：US10377907
申请日：2003-02-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.
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公开(公告)号：US06904577B2
公开(公告)日：2005-06-07
申请号：US10406732
申请日：2003-04-02
IPC分类号： G01R31/3183 , G06F11/00 , G06F11/26 , G06F17/50 , G06T17/05
CPC分类号： G01R31/318357 , G01R31/318364 , G06F11/26 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
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