公开(公告)号：US5682516A

公开(公告)日：1997-10-28

申请号：US205023

申请日：1994-03-01

申请人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

发明人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

IPC分类号： G06F12/08 ,  G06F13/368 ,  H04L29/06 ,  G06F13/18

CPC分类号： G06F12/0831 ,  G06F13/368 ,  H04L29/06 ,  G06F12/0813

摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

摘要翻译： 公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。 所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。 特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

公开(公告)号：US5572702A

公开(公告)日：1996-11-05

申请号：US202790

申请日：1994-02-28

申请人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F13/1668

摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

公开(公告)号：US5797026A

公开(公告)日：1998-08-18

申请号：US921845

申请日：1997-09-02

申请人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831

摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.

摘要翻译： 一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。 处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。 自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

公开(公告)号：US5909699A

公开(公告)日：1999-06-01

申请号：US672422

申请日：1996-06-28

申请人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F13/1668

摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

摘要翻译： 总线上代理发出的内存请求在保持缓存一致性的同时得到满足。 请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。 总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。 可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。 侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。 在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。 在写请求的情况下，请求代理随着请求传送总线上的写数据。 该写入数据由临时存储数据的存储单元和监听代理二者检索。 随后，窥探代理通过总线传输整个高速缓存行。 存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

公开(公告)号：US5623628A

公开(公告)日：1997-04-22

申请号：US205040

申请日：1994-03-02

申请人： James M. Brayton ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Glenn J. Hinton

发明人： James M. Brayton ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/18 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F13/18 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3834

摘要： A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

摘要翻译： 一种计算机系统及其执行的方法，具有用于确保在多级分层存储器系统中的各种级别的高速缓存之间的数据的一致性的机制。 高速缓存一致性机制包括一个外部总线请求队列及其相关联的机制，它们协调监视和控制诸如读请求和写请求之类的数据请求的发布到外部总线上。 计算机系统包括一个或多个具有这一一致性机制的CPU。

公开(公告)号：US5535345A

公开(公告)日：1996-07-09

申请号：US241964

申请日：1994-05-12

申请人： Matthew A. Fisch ,  James M. Brayton ,  Ajay Malhotra

发明人： Matthew A. Fisch ,  James M. Brayton ,  Ajay Malhotra

IPC分类号： G06F15/17 ,  H01J13/00

CPC分类号： G06F15/17

摘要： In accordance with the preferred embodiment of the present invention, a bus interface unit of a microprocessor is provided with a Micro Request Sequencer (EBMRS) disposed between a bus scheduling queue (EBBQ) and external bus control logic (EBCTL). Under normal bus request traffic, the EBMRS is effectively transparent and allows normal communication between the EBCTL and the EBBQ. However, for misaligned bus transactions, which comprise memory accesses that cross a bus width boundary, the EBMRS intercepts such transactions for special sequencing, while blocking any further requests from the EBBQ. The EBMRS separates each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus. It then issues the first split request to the EBCTL for processing on the external bus. External bus agents involved with processing of the split requests then return first response information regarding the completion of the first split request. If the first response information indicates that the first split request will complete without being deferred or retried, the EBMRS issues the second split request to the EBCTL for processing on the external bus. Upon the receipt of second response information for the second split request indicating that the second split request is guaranteed to complete without being deferred or retried, the EBMRS then issues any further transaction requests received from the EBBQ without jeopardizing the order dependency of the split requests or subsequent bus transaction requests buffered in the EBBQ.

摘要翻译： 根据本发明的优选实施例，微处理器的总线接口单元设置有布置在总线调度队列（EBBQ）和外部总线控制逻辑（EBCTL）之间的微请求排序器（EBMRS）。 在正常总线请求流量下，EBMRS有效透明，允许EBCTL和EBBQ之间进行正常通信。 然而，对于包含跨越总线宽度边界的存储器访问的未对齐总线事务，EBMRS拦截这种事务以进行特殊排序，同时阻止来自EBBQ的任何进一步的请求。 EBMRS将每个不对齐的总线事务请求分成至少第一和第二分组事务请求，每个分离请求形成不跨越外部总线的数据总线宽度边界的存储器访问。 然后，它向EBCTL发出第一个分离请求，以在外部总线上进行处理。 涉及处理分离请求的外部总线代理然后返回关于完成第一个分离请求的第一响应信息。 如果第一个响应信息指示第一个分离请求将在不延迟或重试的情况下完成，则EBMRS向EBCTL发出第二个分离请求以在外部总线上进行处理。 在接收到指示第二分裂请求被保证完成而不被延迟或重试的第二分组请求的第二响应信息时，EBMRS然后发出从EBBQ接收的任何进一步的事务请求，而不会危害分离请求的顺序依赖性， 在EBBQ中缓存的后续总线事务请求。