公开(公告)号：US5572702A

公开(公告)日：1996-11-05

申请号：US202790

申请日：1994-02-28

申请人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F13/1668

摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

公开(公告)号：US5797026A

公开(公告)日：1998-08-18

申请号：US921845

申请日：1997-09-02

申请人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831

摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.

摘要翻译： 一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。 处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。 自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

公开(公告)号：US5909699A

公开(公告)日：1999-06-01

申请号：US672422

申请日：1996-06-28

申请人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

发明人： Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Amit A. Merchant ,  Matthew A. Fisch ,  James M. Brayton

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F13/1668

摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

摘要翻译： 总线上代理发出的内存请求在保持缓存一致性的同时得到满足。 请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。 总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。 可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。 侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。 在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。 在写请求的情况下，请求代理随着请求传送总线上的写数据。 该写入数据由临时存储数据的存储单元和监听代理二者检索。 随后，窥探代理通过总线传输整个高速缓存行。 存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

公开(公告)号：US5682516A

公开(公告)日：1997-10-28

申请号：US205023

申请日：1994-03-01

申请人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

发明人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

IPC分类号： G06F12/08 ,  G06F13/368 ,  H04L29/06 ,  G06F13/18

CPC分类号： G06F12/0831 ,  G06F13/368 ,  H04L29/06 ,  G06F12/0813

摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

摘要翻译： 公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。 所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。 特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

公开(公告)号：US5784579A

公开(公告)日：1998-07-21

申请号：US709214

申请日：1996-09-06

申请人： Stephen S. Pawlowski ,  Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Matthew A. Fisch ,  Peter D. MacWilliams

发明人： Stephen S. Pawlowski ,  Nitin V. Sarangdhar ,  Michael W. Rhodehamel ,  Matthew A. Fisch ,  Peter D. MacWilliams

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/387 ,  G06F13/4027 ,  G06F13/4217

摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.

摘要翻译： 动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。 耦合到总线的代理包括发射机和接收机。 发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。 接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

公开(公告)号：US5778441A

公开(公告)日：1998-07-07

申请号：US764663

申请日：1996-12-11

申请人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Matthew A. Fisch

发明人： Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Matthew A. Fisch

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1652

摘要： Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.

摘要翻译： 响应于微处理器对于总线锁定访问的请求，锁定变量的原子性被保留在计算机系统中，无论锁定变量是在两个高速缓存行之间分离还是在单个高速缓存行内。 允许通过与发出访问的微处理器相同的集群内的可缓存区域来满足的非分裂锁总线访问，而不管下一级总线的所有权是否可用。 如果在集群内不能满足非分裂锁访问，则获得下一级总线的所有权（如果可用）以满足访问。 类似地，如果可以获得第二级总线的所有权，则分裂锁定访问可以完成。 但是，如果第二级总线所有权不可用，则无论同一个集群中的可缓存区域是否满足请求，则会中断拆分锁访问。

公开(公告)号：US5581782A

公开(公告)日：1996-12-03

申请号：US538597

申请日：1995-10-03

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

IPC分类号： G06F13/36 ,  G06F13/364 ,  H04L12/403 ,  G06F13/18

CPC分类号： G06F13/364 ,  G06F13/36 ,  H04L12/403 ,  H04L12/4015

摘要： A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner). The symmetric owner is allowed to take ownership of the bus and issue a transaction on the bus provided no other action of higher priority is preventing the use of the bus. A symmetric owner can maintain ownership without re-arbitrating if the transaction is either a bus-locked or a burst access transaction. The priority agent(s) has higher priority than the symmetric owner. Once the priority agent arbitrates for the bus, it prevents the symmetric owner from issuing any new transactions on the bus unless the new transaction is part of an ongoing bus-locked operation.

摘要翻译： 一种用于提供包括对优先代理的支持的高性能对称仲裁协议的系统和方法。 总线仲裁协议支持两类总线代理：对称代理和优先代理。 对称代理使用循环算法支持公平的分布式仲裁。 每个对称代理都具有在复位时分配的唯一代理ID。 该算法按照循环顺序排列对称代理。 每个对称代理还维持忙或空闲的总线所有权状态以及在下一个仲裁事件中反映具有最低优先级的对称代理的旋转ID。 在仲裁事件中，优先级最高的对称代理成为对称所有者。 然而，对称所有者不一定是总线总线所有者（即，优先代理可以是总线总线所有者）。 允许对称所有者获得公共汽车的所有权，并在公共汽车上发出交易，只要没有更高优先级的其他动作阻止使用公共汽车。 如果事务是总线锁定或突发访问事务，对称所有者可以维护所有权而不重新仲裁。 优先级代理的优先级高于对称所有者。 一旦优先级代理对总线进行仲裁，就可以防止对称所有者在总线上发出任何新的事务，除非新的事务是持续的总线锁定操作的一部分。

公开(公告)号：US5623628A

公开(公告)日：1997-04-22

申请号：US205040

申请日：1994-03-02

申请人： James M. Brayton ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Glenn J. Hinton

发明人： James M. Brayton ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/18 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F13/18 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3834

摘要： A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

摘要翻译： 一种计算机系统及其执行的方法，具有用于确保在多级分层存储器系统中的各种级别的高速缓存之间的数据的一致性的机制。 高速缓存一致性机制包括一个外部总线请求队列及其相关联的机制，它们协调监视和控制诸如读请求和写请求之类的数据请求的发布到外部总线上。 计算机系统包括一个或多个具有这一一致性机制的CPU。

公开(公告)号：USRE38388E1

公开(公告)日：2004-01-13

申请号：US09882444

申请日：2001-06-14

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

IPC分类号： H04L12417

CPC分类号： G06F13/368 ,  G06F13/4213

摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

公开(公告)号：US5809524A

公开(公告)日：1998-09-15

申请号：US822044

申请日：1997-03-24

申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/123 ,  G06F12/0831

摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

摘要翻译： 一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。 该接口包括地址总线，数据总线和状态总线。 地址总线将请求的地址从控制器传送到高速缓冲存储器。 数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。 状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。 在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。